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general description the MAX1463 is a highly integrated, low-power, two- channel sensor signal processor optimized for industri- al and process control applications such as pressure sensing and compensation, rtd and thermal-couple linearization, weight sensing and classification, and remote process monitoring with limit indication. the MAX1463 accommodates sensors with outputs ranging from 1mv/v to 1v/v and supports both pro- grammable current and voltage sensor excitation. the MAX1463 provides amplification, calibration, signal lin- earization, and temperature compensation that enable an overall performance approaching the inherent repeatability of the sensor without requiring any exter- nal trim components. two 16-bit voltage output dacs and two 12-bit pwms can be used to indicate each of the temperature-com- pensated sensor signals independently, as a sum or difference signal, or user-defined relationship between each signal and temperature. uncommitted op amps are available for buffering the dac outputs, driving heavier external loads, or providing additional gain and filtering. the MAX1463 incorporates a 16-bit cpu, user-pro- grammable 4kb of flash program memory, 128 bytes of flash user information, one 16-bit adc, two 16-bit dacs, two 12-bit pwm digital outputs, four rail-to-rail op amps, one spi-compatible interface, two gpios, and one on-chip temperature sensor. the MAX1463 operates from a single 5.0v supply and is packaged for automotive, industrial, and commercial temperature ranges in a 28-pin ssop package. applications pressure sensor signal conditioning weight measurement systems thermocouple and rtd linearization transducers and transmitters process indicators calibrators and controllers gmr and mr magnetic direction sensors features programmable amplification, calibration, linearization, and temperature compensation two differential or four single-ended sensor input channels accommodates sensor output sensitivities from 1mv/v to 1v/v two dac/pwm output signal channels 4?0ma output capability 4kb of flash memory for code and coefficients 128 bytes of flash memory for user information integrated temperature sensor flexible dual op-amp blocks programmable sensor input gain and offset programmable sensor sampling rate and resolution programmable current excitation source for bridge sensors buffered 1.25v output reference no external trim components required MAX1463 low-power two-channel sensor signal processor ________________________________________________________________ maxim integrated products 1 ordering information 19-2549; rev 0; 8/02 for pricing, delivery, and ordering information, please contact maxim/dallas direct! at 1-888-629-4642, or visit maxim? website at www.maxim-ic.com. * dice are tested at t a = +25?, dc parameters only. functional diagram and detailed block diagram appear at end of data sheet. rail-to-rail is a registered trademark of nippon motorola, ltd. spi is a trademark of motorola, inc. part temp range pin-package MAX1463cai 0 c to +70 c 28 ssop MAX1463c/w* 0 c to +70 c die MAX1463eai -40 c to +85 c 28 ssop MAX1463aai -40 c to +125 c 28 ssop 28 27 26 25 24 23 22 21 20 19 18 17 16 15 1 2 3 4 5 6 7 8 9 10 11 12 13 14 out2sm amp2m amp2p out2lg isrc inp1 v ddf inm1 inp2 inm2 vref v ss gpio2 gpio1 v ss sclk di do cs ckio cksel n.c. v dd vbg out1lg amp1p amp1m out1sm ssop top view MAX1463 pin configuration
MAX1463 low-power two-channel sensor signal processor 2 _______________________________________________________________________________________ absolute maximum ratings electrical characteristics (v dd = 5.0v, v ss = 0v, f clk = 4.0mhz, t a = t min to t max . typical values are at t a = +25 c, unless otherwise noted.) (note 1) stresses beyond those listed under ?bsolute maximum ratings?may cause permanent damage to the device. these are stress rating s only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specificatio ns is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability. v dd - v ss ...............................................................-0.3v to +6.0v all other pins to v ss ...................................-0.3v to (v dd + 0.3v) continuous power dissipation (t a = +70 c) 28-pin ssop (derate 9.5mw/ c above +70 c) ..........762mw operating temperature ranges (t min to t max ) MAX1463cai .....................................................0 c to +70 c MAX1463eai...................................................-40 c to +85 c MAX1463aai ................................................-40 c to +125 c MAX1463c/w.....................................................0 c to +70 c junction temperature ......................................................+150 c storage temperature range .............................-65 c to +150 c lead temperature (soldering, 10s) ................................ +300 c parameter symbol conditions min typ max units supply supply voltage v dd v ss = 0v 4.5 5.0 5.5 v base operating current i bo cpu stopped (note 2) 640 715 785 a cpu current i cpu all modules off, cpu = on, additive to i bo (note 3) 650 820 995 a all modules off, adc = on, adc clk = 1mhz, additive to i bo ; the cpu and adc are not on at the same time (note 3) 840 1035 1150 adc current i adc all modules off, adc = on, adc clk = 7khz, additive to i bo ; the cpu and adc are not on at the same time (note 3) 510 720 850 a dac current i dacn all modules off, dac = on, additive to i bo, (n = 1 or 2) (note 4) 400 470 520 a large op-amp current i oplgn all modules off, cpu stopped, large op amp = on (n = 1 or 2) 350 585 700 a small op-amp current i opsmn all modules off, cpu stopped, small op amp = on (n = 1 or 2) 130 175 210 a analog input pga[4:0] = 00000, clk[2:0] = 000 4 m ? pga[4:0] = 01010 , clk[2:0] = 000 100 pga[4:0] = 11110, clk[2:0] = 000 62.5 k ? pga[4:0] = 00000, clk[2:0] = 011 32 m ? pga[4:0] = 01010, clk[2:0] = 011 800 pga[4:0] = 11110, clk[2:0] = 011 500 k ? pga[4:0] = 00000, clk[2:0] = 110 256 pga[4:0] = 01010, clk[2:0] = 110 6.4 differential input impedance (inp1 to inm1 and inp2 to inm2) r din pga[4:0] = 01000, clk[2:0] = 110 4 m ?
MAX1463 low-power two-channel sensor signal processor _______________________________________________________________________________________ 3 parameter symbol conditions min typ max units pga[4:0] = 00000, clk[2:0] = 000 2 m ? pga[4:0] = 01010 , clk[2:0] = 000 50 pga[4:0] = 11110, clk[2:0] = 000 31.2 k ? pga[4:0] = 00000, clk[2:0] = 011 16 m ? pga[4:0] = 01010, clk[2:0] = 011 400 pga[4:0] = 11110, clk[2:0] = 011 250 k ? pga[4:0] = 00000, clk[2:0] = 110 128 pga[4:0] = 01010, clk[2:0] = 110 3.2 single-sided input impedance (inp1 to v ss , inm1 to v ss , inp2 to v ss , inp2 to v ss ) r sin pga[4:0] = 01000, clk[2:0] = 110 2 m ? common-mode rejection ratio cmrr common-mode voltage v cm = v ss to v dd 90 db differential signal-gain range selectable in 17 steps (note 5) 0.94 240 pga[4:0] = 00000 0.90 0.94 1.0 pga[4:0] = 00001 7.0 7.4 8.0 pga[4:0] = 01010 68 73 78 pga[4:0] = 10100 125 133 143 differential signal gain a vdiff pga[4:0] = 11110 220 240 260 v/v gain-error temperature coefficient getc adc pga[4:0] = 00000 -8 ppm/ c coarse-offset dac resolution 3-bit plus sign 4 bits pga[4:0] = 00000 to 01000 130 135 140 pga[4:0] = 01010 to 10000 256 266 276 coref = v dd , co[3:0] = 0111 pga[4:0] = 10100 to 11110 450 481 510 pga[4:0] = 00000 to 01000 55 60 65 pga[4:0] = 01010 to 10000 107 117 127 coref = v dd , co[3:0] = 0011 pga[4:0] = 10100 to 11110 180 210 240 pga[4:0] = 00000 to 01000 0510 pga[4:0] = 01010 to 10000 3915 effective offset adjustment at the adc input oa adc coref = v dd , co[3:0] = 0000 pga[4:0] = 10100 to 11110 -4 +8 +20 % of adc ref electrical characteristics (continued) (v dd = 5.0v, v ss = 0v, f clk = 4.0mhz, t a = t min to t max . typical values are at t a = +25 c, unless otherwise noted.) (note 1)
MAX1463 low-power two-channel sensor signal processor 4 _______________________________________________________________________________________ parameter symbol conditions min typ max units pga[4:0] = 00000 to 01000 81216 pga[4:0] = 01010 to 10000 17 23 30 coref = v dd , co[3:0] = 1000 pga[4:0] = 10100 to 11110 23 33 43 pga[4:0] = 00000 to 01000 -50 -44 -40 pga[4:0] = 01010 to 10000 -94 -87 -80 coref = v dd , co[3:0] = 1011 pga[4:0] = 10100 to 11110 -185 -169 -155 pga[4:0] = 00000 to 01000 -124 -117 -110 pga[4:0] = 01010 to 10000 -250 -238 -225 effective offset adjustment at the adc input oa adc coref = v dd , co[3:0] = 1111 pga[4:0] = 10100 to 11110 -475 -445 -415 % of adc ref small op amp input offset voltage v os _ sm 07mv input bias current i b _ sm 1 na dc gain a vol _ sm outnsm = 0.5v to 4.5v (n = 1 or 2), r load = 4.9 output high voltage v oh _ sm r load = 4.7k ? to v ss 4.85 v r load = 0.1 output low voltage v ol _ sm r load = 4.7k ? to v dd 0.15 v output source current i src _ sm v outnsm = v oh_sm , r load = 4.7k ? to v ss -1.04 ma output sink current i snk _ sm v outnsm = v ol_sm , r load = 4.7k ? to v dd 1.04 ma maximum output load capacitance c l _ sm r load = , phase margin > 55 electrical characteristics (continued) (v dd = 5.0v, v ss = 0v, f clk = 4.0mhz, t a = t min to t max . typical values are at t a = +25 c, unless otherwise noted.) (note 1)
MAX1463 low-power two-channel sensor signal processor _______________________________________________________________________________________ 5 parameter symbol conditions min typ max units large op amp input offset voltage v os _ lg 04mv input bias current i b _ lg 225 na dc gain a vol _ lg outnlg = 0.5v to 4.5v (n = 1 or 2), r load = ? to v ss 4.90 v r load = ? to v dd 0.12 v output source current i src _ lg v outnlg = v oh_lg , r load = 1k ? to v ss -4.9 ma output sink current i snk _ lg v outnlg = v ol_lg , r load = 1k ? to v dd 4.9 ma maximum output load capacitance c l _ lg r load = , phase margin > 55 op-amp switch analog signal range v sw v ss v dd v on-resistance r on 5k ? off-isolation v iso 80 db digital-to-analog converter resolution res dac 16 bits integral nonlinearity inl dac 3 bits differential nonlinearity dnl dac 1 bits offset error v dac os dac ref = v dd , dac data = 0000h v dd / 2 - 0.05 v dd / 2 + 0.05 v bit weight bw dac dac ref = 5vdc 91.55 v/lsb power-supply rejection ratio psrr dac at dc, dac ref = v ref 60 db output noise on dac dac buffer is the small op amp 3 lsb output settling time st dac to 0.1% of final value 250 s pulse-width modulator resolution res pwm (note 6) 12 bits period p pwm f clk = 4.0 mhz 8.192 ms electrical characteristics (continued) (v dd = 5.0v, v ss = 0v, f clk = 4.0mhz, t a = t min to t max . typical values are at t a = +25 c, unless otherwise noted.) (note 1)
MAX1463 low-power two-channel sensor signal processor 6 _______________________________________________________________________________________ parameter symbol conditions min typ max units bit weight bw pwm 2 s/lsb offset error v pwm _ os pwm data = 0000h 1 s gain error ge pwm (note 7) 0.025 % output jitter oj pwm 1/4 lsb external reference input reference input range v ref 1.25 v dd v reference input resistance r ref res v ref = 4v, adc = on, dacs = on 100 k ? internal voltage reference internal voltage reference v ir (note 8) 4.2 4.6 5.0 v temperature coefficient tc ir 110 ppm/ c buffered voltage reference output r load = ? to v ss 1.12 v temperature coefficient tc bg 110 ppm/ c current source isrc[2:0] = 000 0 isrc[2:0] = 001 -200 -167 -130 isrc[2:0] = 100 -814 -668 -545 source current i isrc selectable in 8 steps isrc[2:0] = 111 -1420 -1169 -915 a maximum isrc voltage v isrc v dd - 0.85 v temperature sensor -2 mv / c sensitivity sens ts -50 lsb/ c nonlinearity error inl ts 0.5 %fs hysteresis hist ts 0.1 %fs analog-to-digital converter resolution res adc 16 bits integral nonlinearity inl adc 2 bits differential nonlinearity dnl adc 1 lsb adc offset error v adc _ os pga[4:0] = 00000 (0.94), co[3:0] = 0000 (note 9) 4 %fs channel-to-channel offset error matching ? v adc _ os 1 lsb adc offset-supply rejection ratio osrr adc at dc, adc ref = v ref = 5v 52 db adc gain-supply rejection ratio gsrr adc at dc, adc ref = v ref = 5v 96 db electrical characteristics (continued) (v dd = 5.0v, v ss = 0v, f clk = 4.0mhz, t a = t min to t max . typical values are at t a = +25 c, unless otherwise noted.) (note 1)
MAX1463 low-power two-channel sensor signal processor _______________________________________________________________________________________ 7 parameter symbol conditions min typ max units digital input (gpio1, gpio2, sclk, di, cksel, ckio, cs ) input high threshold voltage v ih 0.8 x v dd v input low threshold voltage v il 0.2 x v dd v input hysteresis v ihys 0.2 v cksel, cs = v ss -50 input leakage current i in gpio1, gpio2, sclk, di, ckio = v dd 50 a input capacitance c in 5pf digital output (gpio1, gpio2, do, ckio) gpio1, gpio2, do 4.9 r load = ckio (note 10) 4.9 gpio1, gpio2, do 4.6 output voltage high v oh r load = 2k ? to v ss ckio (note 10) 4.6 v gpio1, gpio2, do 0.1 r load = ckio (note 10) 0.1 gpio1, gpio2, do 0.4 output voltage low v ol r load = 2k ? to v dd ckio (note 10) 0.4 v flash memory maximum erase cycles (notes 11, 12) 10k cycles minimum erase time t erase (notes 11, 12) 4.2 ms minimum write time t write (notes 11, 12) 80 s electrical characteristics (continued) (v dd = 5.0v, v ss = 0v, t a = t min to t max , f clk = 4.0mhz. typical values are at t a = +25 c, unless otherwise noted.) (note 1) note 1: current into a pin is defined as positive. current out of a pin is defined as negative. all voltages are referenced to v ss . note 2: all modules are off, except internal reference, oscillator, vbg buffer, and power-on reset (por). isrc is open. note 3: the cpu and adc are not on at the same time. the adc and cpu currents are not additive. note 4: i dacn does not include output buffer currents (i oplgn or i opsmn ). note 5: for gains above 240, an additional digital gain can be provided by the cpu. note 6: the pwm input data is the 12-bit left-justified data in the 16-bit input field. note 7: pwm gain error measured as: note 8: the internal reference voltage has a nominal value of 5v (4 ? v bg ) even when v dd is greater or less than 5vdc. note 9: input-referred offset error is the adc offset error divided by the pga gain. note 10: when the ckio pin is configured in output mode to observe the internal oscillator signal, the total current is above the specified limits. note 11: f clk must be within 5% of 4mhz. note 12: allow a minimum elapsed time of 4.2ms when executing a flash erase command, before sending any other command. allow a minimum elapsed time of 80s between flash write commands. ge pwm f xh pwm xh pwm out out = () ? () 00 100 3584 100%
MAX1463 low-power two-channel sensor signal processor 8 _______________________________________________________________________________________ timing characteristics (v dd = +5.0v, v ss = 0v, t a = +25 c, unless otherwise noted.) parameter symbol conditions min typ max units maximum programming temperature t prog 70 c internal oscillator clock frequency f iclk osc[4:0] = 00000 3.4 4.3 5.3 mhz min 0.2 external clock frequency f eclk v cksel = 0 max 5 mhz external master clock input low time f eclkin _ lo t eclk = 1 / f eclk 40 60 % t eclk external master clock input high time f eclkin _ hi t eclk = 1 / f eclk 40 60 % t eclk serial interface (figure 1) sclk setup to falling edge cs t sc 30 ns cs falling edge to sclk rising edge setup time t css 30 ns cs idle time t csi f clk = 4mhz 1.5 s cs period t cs f clk = 4mhz 4 s sclk falling edge to data valid delay t do c load = 200pf 80 ns data valid to sclk rising edge setup time t ds 30 ns data valid to sclk rising edge hold time t dh 30 ns sclk high pulse width t ch 100 ns sclk low pulse width t cl 100 ns cs rising edge to sclk rising edge hold time t csh 30 ns cs falling edge to output enable t dv c load = 200pf 25 ns cs rising edge to output disable t tr c load = 200pf 25 ns
MAX1463 low-power two-channel sensor signal processor _______________________________________________________________________________________ 9 typical operating characteristics (v dd = 5.0v, t a = +25 c, unless otherwise noted.) supply current vs. supply voltage MAX1463 toc01 supply voltage, v dd (v) supply current, i dd (ma) 5.3 5.1 4.7 4.9 2.30 2.35 2.40 2.45 2.50 2.55 2.60 2.65 2.25 4.5 5.5 t a = +25 c t a = +125 c t a = -40 c cpu on 2% of time adc on 98% of time adc clk = 1mhz dac1 on small op amp on supply current vs. external clock frequency MAX1463 toc02 external clock frequency (mhz) supply current, i dd (ma) 4.5 4.0 3.5 2.05 2.10 2.15 2.20 2.25 2.30 2.35 2.40 2.45 2.50 2.00 3.0 5.0 cpu on 2% of time adc on 98% of time adc clk = 1mhz dac1 on small op amp on module current vs. temperature MAX1463 toc03 temperature ( c) module current (ma) 98 70 43 15 -13 0.7 0.9 1.1 1.3 1.5 1.7 1.9 2.1 2.3 2.5 0.5 -40 125 dac + large op amp adc dac + small op amp base base operating current vs. supply voltage MAX1463 toc04 supply voltage, v dd (v) base operating current, i bo (ma) 5.3 5.1 4.7 4.9 0.67 0.69 0.71 0.73 0.75 0.77 0.79 0.81 0.65 4.5 5.5 t a = +25 c t a = +125 c t a = -40 c adc output error vs. supply voltage MAX1463 toc05 supply voltage, v dd (v) adc output error (%fs) 5.3 5.1 4.7 4.9 -0.03 -0.02 -0.01 0 0.01 0.02 0.03 0.04 -0.04 4.5 5.5 adc input = 0.75 x v dd adc input = 0.5 x v dd adc input = 0 adc input = -0.75 x v dd adc input = -0.5 x v dd adc ref = v dd pga[4:0] = 00000 adc inl MAX1463 toc06 1.0 0.5 -0.5 0 -1.0 input voltage normalized to full scale adc nonlinearity error (%fs) -0.004 -0.002 0 0.002 0.004 0.006 -0.006 pga[4:0] = 01000
internal oscillator frequency vs. supply voltage MAX1463 toc12 supply voltage, v dd (v) internal oscillator frequency (mhz) 5.3 5.1 4.9 4.7 3.85 3.90 3.95 4.00 4.05 4.10 4.15 3.80 4.5 5.5 t a = -40 c t a = +125 c t a = +25 c oscillator frequency trimmed to 4mhz at +25 c, v dd = 5v temperature sensor output vs. temperature MAX1463 toc13 temperature ( c) temperature sensor output (adc code) 98 70 43 15 -13 10000 12000 14000 16000 18000 8000 -40 125 MAX1463 low-power two-channel sensor signal processor 10 ______________________________________________________________________________________ adc dnl MAX1463 toc07 input voltage normalized to full scale adc dnl error (lsb) 0.5 0 -0.5 -3 -2 -1 0 1 2 3 4 -4 -1.0 1.0 pga[4:0] = 01000 dac inl MAX1463 toc08 input normalized to full scale dac nonlinearity error (%fs) 0.6 0.4 -0.6 -0.4 -0.2 0 0.2 -0.03 -0.02 -0.01 0 0.01 0.02 0.03 0.04 -0.04 -0.8 0.8 dac dnl MAX1463 toc09 input voltage normalized to full scale dac dnl error (lsb) 0.6 0.4 0.2 0 -0.2 -0.4 -0.6 -2 -1 0 1 2 3 -3 -0.8 0.8 dac dynamic response 200 s/div 4 5 0 2 3 1 1v/div dac code = 4000h dac code = c000h MAX1463 toc10 dac ratiometricity error vs. supply voltage MAX1463 toc11 supply voltage, v dd (v) error (%fs) 5.3 5.1 4.9 4.7 -0.04 -0.03 -0.02 -0.01 0 0.01 0.02 0.03 0.04 0.05 -0.05 4.5 5.5 dac input = 5555ch (4.5v at v dd = 5v) dac input = 0000ch (2.5v at v dd = 5v) dac input = aaabch (0.5v at v dd = 5v) typical operating characteristics (continued) (v dd = 5.0v, t a = +25 c, unless otherwise noted.)
MAX1463 low-power two-channel sensor signal processor ______________________________________________________________________________________ 11 pin description pin name function 1 out1sm small op amp 1 output 2 amp1m op amp 1 negative input 3 amp1p op amp 1 positive input 4 out1lg large op amp 1 output 5 vbg buffered bandgap voltage output 6v dd positive supply voltage input. bypass v dd to v ss with a 0.f ceramic capacitor. 7 n.c. no connection 8 cksel clock select digital input 9 ckio clock digital input/output 10 cs spi chip select digital input. active low. 11 do spi data output 12 di spi data input 13 sclk spi interface clock 14, 18 v ss negative power-supply input 15 v ddf positive supply voltage for flash memory. bypass v ddf to v ss with a 0.47f ceramic capacitor. 16 gpio1 general-purpose digital input/output 1 17 gpio2 general-purpose digital input/output 2 19 vref external reference voltage input for adc and dacs 20 inm2 negative input for adc channel 2 21 inp2 positive input for adc channel 2 22 inm1 negative input for adc channel 1 23 inp1 positive input for adc channel 1 24 isrc current output for sensor excitation 25 out2lg large op amp 2 output 26 amp2p op amp 2 positive input 27 amp2m op amp 2 negative input 28 out2sm small op amp 2 output
MAX1463 low-power two-channel sensor signal processor 12 ______________________________________________________________________________________ typical application circuit analog ratiometric output configuration (figure 2) pro- vides an output that is proportional to the power-supply voltage. ratiometricity is an important consideration for automotive, battery-operated instruments, and some industrial applications. detailed description the MAX1463 is a highly integrated, low-power, two- channel sensor signal processor optimized for industri- al and process control applications, such as pressure sensing and compensation, rtd and thermal-couple linearization, weight sensing and classification, and remote process monitoring with limit indication. the MAX1463 incorporates a 16-bit cpu, user-pro- grammable 4kb of flash memory, 128 bytes of flash user information, 16-bit adc, two 16-bit dacs, two 12-bit pwm digital outputs, four rail-to-rail op amps, spi interface, two gpios, and one on-chip temperature sensor. each sensor signal can be amplified, compensated for temperature, linearized, and the offset and full scale can be adjusted to the desired value. the MAX1463 can provide outputs as analog voltage (dac) or digital (pwm, gpios), or simple on/off alarm indication (gpios). the uncommitted op amps can be used to provide 4 20ma outputs or for additional gain and fil- tering. each dac output is routed to either a small or large op amp. large op amps are capable of driving heavier external loads. the unused circuit functions can be turned off to save power. all sensor linearization and on-chip temperature com- pensation is done by a user-defined algorithm stored in flash memory. the user-defined algorithm is pro- grammed over the serial interface and stored in 4kb of integrated flash memory. the MAX1463 uses an internal 4mhz oscillator or an externally supplied 4mhz clock. cpu code execution and adc operation is fully synchronized to minimize the noise interference of a cpu-based sensor proces- sor system. the internal clock can be routed off chip for driving external circuit components to maintain system synchronization and to avoid clock-beat noise often found in multiclock systems. the cpu sequentially exe- cutes instructions stored in flash memory. sensor input the MAX1463 provides two differential signal inputs, inp1-inm1 and inp2-inm2. these inputs can also be configured as four singled-ended signals. each input can have a common-mode range from v dd to v ss and a programmable gain range of 0.94v/v to 240v/v. the differential input signals are summed with the output of the coarse offset dac (co dac) for offset correction prior to being amplified by the programmable gain amplifier (pga). the resulting signal is applied to the differential input of the adc for conversion. do di sclk cs t css t cl t ch t csh t sc t cs t ds t dh t ds t dh t csi t css t cl t ch t sc t csh t do t tr t dv t dv t do t tr figure 1. serial interface timing diagram
MAX1463 low-power two-channel sensor signal processor ______________________________________________________________________________________ 13 the cpu can be programmed to measure one or two differential inputs plus the internal temperature sensor defined in user-supplied algorithm. for example, the differential inputs may be measured many times while the temperature may be measured less frequently. on-chip temperature sensing the on-chip temperature sensor is a diode that changes -2mv/ c over the operating range. the adc converts the temperature sensor in a similar manner as the sensor inputs. during an adc conversion of the temperature sensor, the adc automatically uses the internal 1.25v reference as the adc full-scale reference. the tempera- ture data format is 15-bit plus sign in two s complement format. there is no programmable gain adjustment for the temperature sensor input. offset compensation by the co dac is provided so that the nominal temperature measurement can be centered at the adc output mid- scale value. additional digital gain and offset correction can be provided by the cpu. output format there are two output modules in the MAX1463 dop1 (dac op amp pwm 1) and dop2 (dac op amp pwm 2). each of the dop modules contains a 16-bit dac, a 12-bit digital pwm converter, a small op amp, and a large op amp with high-output drive capability. each module can be configured in several different modes to suit a wide range of output signal requirements. either the dac or the pwm can be selected as the primary output signal. the dac output signal must be routed to one of the two op amps before being made available to a device pin. see the dac, op amp, pwm modules section for details. additional digital outputs are avail- able on the gpios; 4 20ma output format can be accomplished by using the unrouted op amp. initialization a user-defined initialization routine is required to con- figure the oscillator frequency and, if necessary, vari- ous analog modules, e.g., pga gain, adc resolution, adc clock settings, etc. after the initialization routine, the cpu can start execution of the main program. power-on reset the MAX1463 contains a por circuit to disable cpu execution until adequate v dd voltage is available for operation. once the power-on state has been reached, the MAX1463 is kept under reset condition for 250s before the cpu starts execution. below the v dd thresh- old, all internal cpu registers are set to their por default state. power-on control bits for internal modules are reset to the off condition. cpu architecture the cpu provides a wide range of functionality to be incorporated in an embedded system. the cpu can compensate nonlinear and temperature-dependent sen- sors, check for over/underlimit conditions, output sensor or temperature data as an analog signal or pulse-width- modulated digital signal, and execute control strategies. the cpu can perform a limited amount of signal pro- cessing (filtering). a timer is included so that uniform sampling (equally spaced adc conversions) of the input sensors can be performed. 5 vdc v dd sensor v ss v ddf outnsm out 0.47 f 0.1 f 100pf inpn inmn gnd 100 ? MAX1463 figure 2. basic bridge sensor ratiometric output configuration
MAX1463 low-power two-channel sensor signal processor 14 ______________________________________________________________________________________ the cpu registers and ports are implemented in volatile, static memory. there are several registers con- tained in various peripheral modules that provide mod- ule configuration settings, control functions, and data. these module registers are accessible through an indi- rect addressing scheme as described in detail in the cpu registers, cpu ports, and modules sections. figure 3 shows the cpu architecture. cpu registers the MAX1463 incorporates a cpu with 16 internal reg- isters. all of the cpu registers have a 16-bit data word width. five of the 16 registers have predefined function- al operation dependent on the instruction being execut- ed. the remaining registers are general purpose. the cpu registers are embedded in the cpu itself and are not all directly accessible by the serial interface. the accumulator register (a), the pointer register (p), and the instruction (flash data) can be read through the serial interface when the cpu is halted. this enables a single-step mode of code execution to ease code writing and debugging. a special program instruction sequence is required to observe the other cpu registers. table 1 lists the cpu registers. cpu ports the MAX1463 incorporates 16 cpu ports that are directly accessible by the serial interface. all the cpu ports have a 16-bit data-word width. the contents of the ports can be read and written by transferring data to and from the accumulator register (a) using the rdx and wrx instruc- tions. no other cpu instructions act on the cpu ports. three cpu ports pd, pe, and pf have uniquely defined operation for reading and writing data to and from the peripheral modules. all cpu ports are static and volatile. modules the MAX1463 modules are the functional blocks used to process analog and digital signals to and from the cpu. each module is addressed through cpu ports pd, pe, and pf, as described in the cpu ports section. all mod- ules use static, volatile registers for data retention. there are three types of module registers: configuration, data, and control. they are used to put a module into a partic- ular mode of operation. configuration registers hold con- figuration bits that control static settings such as pga gain, coarse offset, etc. data registers hold input data such as dac and pwm input words or output data such as the result of an adc conversion. control registers are used to initiate a process (such as an adc conversion or a timer) or to turn modules on and off (such as op amps, dac outputs, pwm outputs, etc.) adc module the adc module (figure 4) contains a 9-bit to 16-bit sigma-delta converter with multiplexed differential and single-ended signal inputs, a co dac, four reference voltage inputs, two differential or four single-ended external inputs, and 15 single-ended internal voltages for measurement. the adc output data is 16-bit two s complement format. the conversion channel, modes, and reference sources are all set in adc configuration registers. the conversion time is a function of the selected resolution and adc clock frequency. the cpu can be programmed to convert any of the inputs and the internal temperature sensor in any desired sequence. for example, the differential inputs may be converted many times and conversions of temperature performed less frequently. the adc uses the internal 1.25v bandgap reference (v bg ) when converting the temperature input. for any other conversions, the adc reference can be selected as v dd for conversions ratiometric to the power supply, vref pin for conversions relative to an external voltage, and vbgx4, which is an internally generated pseudo 5.0v reference source. the adc voltage reference is also used by the co dac to main- tain a signal conversion that is ratiometric to the select- ed reference source. flash memory (4kb) serial interface sclk di do cs r0 pointer (p) r1 accumulator (a) r2 r3 multiplicand (n) r4 multiplier (m) r6 r7 r8 r9 ra rb rc rd re rf p0 p1 p2 p1 p3 p4 p5 p6 p7 p8 pa pb pc pd pe pf cpu registers instruction cpu flash data address cpu ports r5 index (i) figure 3. cpu architecture
MAX1463 low-power two-channel sensor signal processor ______________________________________________________________________________________ 15 the four analog inputs (inp1, inm1, inp2, inm2) and several internal circuit nodes can be multiplexed to the adc for a single-ended conversion relative to v ss . the selection of which circuit node is multiplexed to the adc is controlled by the adc_control register. the adc can measure each of the op-amp output nodes with gain for converting user-defined circuits or incorporating system diagnostic test functions. the dac outputs can be con- verted by the adc with either op amp arranged as unity-gain buffers on the dac outputs. the internal power nodes, v dd and v ss , and the bandgap reference vbg can be multiplexed to the adc for conversion as well. these measurement modes are defined and initiat- ed in the adc_control register. see tables 5 and 7 for the single-ended configuration. adc registers the adc module has 10 registers for configuration, control, and data output. there are three conversion channels in the adc; channel 1, channel 2, and tem- perature. channels 1 and 2 are associated with the dif- ferential signal input pairs inp1-inm1 and inp2-inm2, respectively. the temperature channel is associated with the integrated temperature sensor. each channel has two configuration registers (adc_config_na and adc_config_nb where n = 1, 2, or t) for setting con- version resolution, reference input, coarse offsets, etc. the data output from a conversion of channel 1, 2, or t is stored in the respective data output register adc_data_n where n = 1, 2, or t. each of the channels can be used to convert single-ended inputs as listed in table 7. the adc_control register controls which chan- nel is to be converted and what single-ended input, if any, is to be directed to that channel. conversion start to initiate an adc conversion, a word is written to the adc_control register with either cnvt1, cnvt2, or cnvtt bit set to a 1 (table 6). when an adc conver- sion is initiated, the cpu is halted and all cpu and flash activities cease. all cnvt1, cnvt2, and cnvtt bits are cleared after the adc conversion is completed. inp1 inm1 inp2 inm2 co dac ref temperature sensor vss vbg vdd vbg x 4 vref adc inmn vbg outnsm outnlg v dd v ss dacnout via outnsm inpn 1 2 3 4 5 6 7 8 9 no. single ended dacnout via outnlg 00h adc_control 08h adc_config_ta 07h adc_data_t 06h adc_config_2b 09h adc_config_tb 02h adc_config_1a 05h adc_config_2a 04h adc_data_2 03h 01h adc_data_1 adc_config_1b pga m u x vss m u x figure 4. adc module
MAX1463 low-power two-channel sensor signal processor 16 ______________________________________________________________________________________ upon completion of the conversion, the adc result is latched into the respective adc_data_n register. in addition, the convert bits in control register 0 are all reset to zero. the cpu clock is then enabled and pro- gram execution continues single-ended inputs can be converted by either chan- nel 1 or 2 by initiating a conversion on the appropriate channel with the se[3:0] bits set to the desired single- ended input (table 7). several of the single-ended sig- nals are converted with a fixed gain of 0.94v/v or 0.7v/v. the reduced gain of 0.7v/v allows signals at or near the supply rails to be converted without concern of saturation. other single-ended signals can be convert- ed with the full-selectable pga gain range. programmable gain amplifier the gain of the differential inputs and several single- ended inputs can be set to values between 0.94v/v to 240v/v as shown in table 14. the pga bits are set in adc_config_na where n = 1 or 2. the temperature channel has a fixed gain of 0.94v/v. the gain setting must be selected prior to initiating a conversion. adc conversion time and resolution the adc conversion time is a function of the selected resolution, adc clock (f adc ), and system clock (f clk ). the resolution can be selected from 9 bits to 16 bits in the adc_config_na (where n = 1, 2, or t) register by bits resn[2:0]. the lower resolution settings (9 bit) con- vert faster than the higher resolution settings (16 bit). the adc clock f adc is derived from the primary sys- tem clock f clk by a prescalar divisor. the divisor can be set from 4 to 512, producing a range of f adc from 1mhz down to 7.8125khz when f clk is operating at 4.0mhz. other values of f clk produce other scaled values of f adc . systems operating with very-low power consumption benefit from the reduced f adc clock rate. slower clock speeds require less operating current. systems operat- ing from a larger power consumption budget can use the highest f adc clock rate to improve speed perfor- mance over power performance. the adc conversion times for various resolution and clock-rate settings are summarized in table 17. the conversion time is calculated by the formula: t convert = (no. of f adc clocks per conversion) / f adc coarse-input offset adjustment differential input signals that have an offset can be par- tially nulled by the input co dac. an offset voltage is added to the input signal prior to gaining the signal. this allows a maximum gain to be applied to the differential input signal without saturating the conversion channel. the co signal added to the differential signal is a per- centage of the full-scale adc reference voltage as referred to the adc inputs. low pga gain settings add smaller amounts of coarse offset to the differential input. large pga gain settings enable correspondingly larger amounts of coarse offset to be added to the input signal. the co dac also applies to the temperature channel enabling offset compensation of the temperature signal. bias current settings the analog circuitry within the adc module operates from a current bias setting that is programmable. the programmable levels of operation are fractions of the full bias current. the operating power consumption of the adc can be reduced at the penalty of increased conversion times that may be desirable in very-low- power applications. it is recommended operating the adc at full bias when possible. the amount of bias as a fraction of full bias is shown in table 19. the setting is controlled by the biasn[2:0] bits in the adc_con- fig_nb registers where n = 1, 2, or t. reference input voltage select the adc can use one of three different reference volt- age inputs depending on the conversion channel and refn setting as shown in table 20. the differential inputs can be converted ratiometrically to the supply voltage (v dd ), converted ratiometrically to an externally supplied voltage at pin vref, or converted nonratio- metrically using a fixed voltage source derived from the internal bandgap voltage source. the temperature channel is always converted using the internal bandgap- derived voltage source and therefore is not selectable. output sample rate generally, the sensor and temperature data are convert- ed and calculated by an algorithm in the execution loop. the output sample rate of the data depends on the con- version time, the cpu algorithm loop time, and the time to store the result in the dopn_data register. to achieve uniform sampling, the instruction code must be written to provide a consistent algorithm loop time, including branch instruction variations. this total loop time interval should be repeatable for a uniform output rate.
MAX1463 low-power two-channel sensor signal processor ______________________________________________________________________________________ 17 the MAX1463 has a built-in timer that can be used to ensure that the sampling interval is uniform. the time- out value can be set such that the cpu computations and the reading of the serial interface, if required, can be completed before timeout. the gpio pins can be utilized to interrupt an external master microcontroller when the adc conversion is done and/or when the cpu computations are done so that the serial interface can be read quickly. dac, op amp, pwm modules (dopn) there are two output modules in the MAX1463 dop1 and dop2 (figure 5). each of the dop modules con- tains a 16-bit dac, a 12-bit digital pwm converter, a small op amp, and a large op amp with high-output drive capability. switches in the dop module enable a range of interconnectivity among the converters, op amps, and the external pins. either the dac or the pwm may be selected as the primary output signal. the dac output signal is routed to one of the op amps and made available to a device pin. the signal-switch- ing arrangement also allows the unused op amp to be configured as an uncommitted device with all connec- tions available to external pins. the dac and op amps have a power-control bit in the power module. when power is disabled, all circuits in the dac and the op amp are disabled with inputs and outputs in a three-state condition. the proper bits in the power module must be enabled for operation of the dac and op amps. the dac input is a 16-bit two s complement value. an input value of 0000h produces an output voltage of one half of the dac reference voltage. the dac output volt- age increases for positive two s complement numbers, and decreases for negative two s complement numbers. the pwm input is a 12-bit two s complement value. it shares the same input register (dopn_data) as the dac, using the 12 msbs of the 16-bit register. an input value of 000xh produces a 50% duty cycle waveform at the output. the pwm output duty cycle increases for positive two s complement numbers, and decreases for negative two s complement numbers. dop_n configuration options each of the dop modules can be configured in several different modes to suit a wide range of output signal requirements. the functional diagram shows the various switch settings of the configuration and control registers. in situations where configuration settings create a con- flict in switch activation, a priority is applied to the switch logic to prevent the conflict. the dac and/or the pwm can be selected as the out- put signal source. the dac output signal is routed to one of the op amps and made available to a device pin. selecting the large op amp as the dac output dri- ver device enables a robust current drive capability for driving signals into low-impedance loads or across long lengths of wire. the unity-gain buffer configuration is automatically selected, and it provides the dac out- put signal directly to the device pin outnlg. with the large op amp selected, the small op amp can be used as an independent device for external circuit applica- tions when the pwm is disabled. alternatively, the pwm can also be enabled to drive the outnsm device pin, in which case the small op amp is off. selecting the small op amp as the dac output driver device is useful for routing the output signal to other cir- cuits in an embedded control system with high-imped- ance load connections. the unity-gain buffer configuration is automatically selected, and it provides the dac output signal directly to the device pin outnsm. with the small op amp selected, the large op amp can be used as an independent device for external circuit applications when the pwm is disabled. alternatively, the pwm can also be enabled to drive the outnlg device pin, in which case the large op amp is off. the dac has two reference voltage sources available by selection, v dd and vref pin. when the external ref- erence is selected (vref), the actual dac reference is 2 x vref. this allows for some degree of flexibility in the bit weight of the dac. the output of the dac is a voltage proportional to the reference voltage selected, where the proportionality scaling (dac input) is set in the data input register dopn_data. the dop module also provides a 12-bit digital pwm output. at a nominal frequency of 4mhz, the frequency of the pwm is 122hz (pwm period = 8.192ms). the dac and the pwm share the same input register, dopn_data, where the pwm uses the 12 msbs, in two s-complement format. an input of 000xh (4 lsbs are ignored) outputs a 50% duty cycle waveform at the selected output pin (either outnsm or outnlg). the pwm bit weight is 2s, at a nominal frequency of 4mhz. the minimum duty cycle is obtained when the input is 800xh (duty cycle is 0 / 4096 = 0), and the maximum duty cycle at 7ffxh (duty cycle is 4095 / 4096 = 99.98%). a new pwm input word is only effective at the end of a current pwm cycle, therefore preventing pwm glitches on the output.
MAX1463 low-power two-channel sensor signal processor 18 ______________________________________________________________________________________ either the small or the large op amp in the dop module can also be selected as an uncommitted op amp in the MAX1463. the op amps can be configured as a unity- gain buffer, where the output is internally connected to the negative terminal of the op amp, or a stand-alone op amp, where both ampnm and ampnp can be externally con- nected for various analog functions. in the case of a buffer, the device pin ampnm is in high-impedance mode, as the feedback loop around the op amp is connected internally. every function of the dop module can be selected individ- ually (dac, pwm, or op amp), or two out of the three func- tions of the dop module can be selected at the same time (pwm and op amp, or dac and pwm, or dac and op amp), as there are only two output pins for the module, outnsm and outnlg. the various configuration options for the dop are shown in table 21. the pwrdac and pwrop bits are in the power-on control register (address = 31h), and the remaining bits are in the dop registers. timer module the timer module (figure 6) comprises a 12-bit counter, a 4-bit prescalar, and control and configuration registers. when the timer is enabled and initiated, the system master clock, mclk, is prescaled by the divisor set by ps[3:0] in the tmr_config register and the result applied to the 12- bit upcounter. when the counter value matches the time- out value to[11:0] in register tmr_config, bit tmdn is set to 1. the cpu can poll the timer done bit tmdn to check its status. the timer module provides a feature that enables the cpu to be put into a low-power halt mode for the duration of the timer interval. setting the enahalt bit in the tmr_control register while starting the timer (setting the timer enable bit tmen to 1), or while the timer is already enabled and counting halts the cpu at the present instruction until the tmdn bit becomes set by the counter. the cpu com- mences execution with the next instruction. all cpu regis- ters and ports are fully static and retain all data during the elapsed time interval. the time interval between tmen being set to 1, and tmdn being set to 1 can be computed as follows: time interval = (2 / f osc ) x {(prescale value n) x (timeout value to[11:0]) + 1.5} the maximum time interval given f osc = 4mhz clock is 786ms. dac 10h or 13h dopn_data 12h or 15h dopn_config 30h opamp_config 11h or 14h dopn_control ref pwm sw0 sw1 sw2 sw3 sw4 sw5 sw6 sw7 sw8 sw9 vref x 2 vdd outnsm ampnm ampnp outnlg sw10 sw11 sm lg figure 5. dop1 and dop2 modules
MAX1463 low-power two-channel sensor signal processor ______________________________________________________________________________________ 19 power control the power to various subcircuits in the MAX1463 can be turned on and off by cpu control and by the serial inter- face. unused subcircuits and modules can be turned off to reduce power consumption. the default state after power-on is all subcircuits and modules powered off. this enables low-power embedded systems to turn on only the needed modules after exiting a low-power cpu halt timer interval. modules can be turned on and off as needed; however, care must be exercised to allow for module initialization and settling prior to use. oscillator control the MAX1463 has a fully integrated oscillator with a nominal frequency of 4mhz. an external clock source can be used when the clock select pin cksel = 0, operating all internal timing functions. ckio can also be configured as an output source of the internal oscillator clock. this enables synchronization of the MAX1463 with external circuits requiring a clock source. current-source module the current-source module provides a means for exciting resistive bridge sensors with current sourced from v dd . the current source can also be used for general-purpose functions that may be required in an embedded control system. the amount of current sourced is set in the current source_control register. the current source is referenced to the MAX1463 internal bandgap voltage ref- erence and is independent of supply voltage changes. figure 7 is the current-source mode. gpio module the MAX1463 contains two general-purpose digital input/output (gpio) modules, gpio1 and gpio2, which can be written and read by cpu control and by the ser- ial interface. these two i/o pins operate independently of each other. they can be configured as inputs, out- puts, or one input and one output. when configured as an input, there are two modes of sensing digital inputs; as a voltage or logic level, or as an edge detector. in edge-detector mode, either a rising or falling edge can be selected for detection. a bit is set in the gpio con- trol register upon detection of the selected edge. the gpio pins have nominal 100k ? pulldown resistors to v ss as in figure 6. pulldown resistors provide a low logic level when the pin is unconnected. the gpio may also serve as an input pin and its state is read from the gpio control register (tables 28 and 29). when using the gpio pin as a general-purpose output, its output state is defined by writing to the gpio control register. the gpion pins may be configured as an alert output that goes low or high whenever a fault condition hap- pens, e.g., remote sensor line disconnection, overflow conditions in the cpu program execution, etc. all input and output control for the gpio1 and gpio2 pins are contained in gpio1_control (address = 40h) and gpio2_control (address = 41h), respectively. figure 8 shows the gpio1 and gpio2 modules. serial interface timing and operation the MAX1463 serial interface is a high-speed asyn- chronous data input and output communication port, providing access to internal registers for calibration of embedded control sensor systems. all the flash memory is read and write accessible by the serial inter- face for programming of instruction code and calibra- tion coefficients. the MAX1463 serial interface can operate in 4-wire spi-compatible mode or in a 3-wire mode (default on power-up). in 3-wire mode, the di and do lines can be tied together, forming a bidirec- tional data line. the serial interface lines consist of chip-select ( cs ), serial clock (sclk), data in (di), and data out (do). the MAX1463 serial interface is selected by asserting cs low. the serial input clock, sclk, is gated internally to begin sequencing the di input data and outputting the output data onto do. when cs rises, the data that was clocked into di is loaded into an internal register set (irs[7:0]). the MAX1463 chip select line cs cannot be tied low continuously for normal operation. the serial interface can be used both during sensor calibration, as well as during normal operation. each byte of data written into the MAX1463 serial port contains a 4-bit addresses nibble (irsa [3:0]) and a 4- bit data nibble (irsd [3:0]). the irs register holds both the irsd and irsa nibbles as follows: irs [7:0] = irsd [3:0], irsa [3:0] four bytes of irs information must be written into the serial interface to transfer 16 bits of data through irsd into a MAX1463 internal register. all serial data written into the MAX1463 is transferred through the irs regis- ter. the di is read in with the lsb of the irsa nibble first and the msb of the irsd nibble last. figure 9 shows serial interface data input. the irsa bits are decoded to determine which register the irsd bits should be latched into. the irsa bits can address the data holding register (dhr), the port/flash addresses register (pfar), the command register (cr), and the interface mode register (imr). all serial data read from the serial interface is sourced from the 16-bit dhr. any data to be read by the serial interface must first be placed into the internal dhr reg- ister before being accessible for reading by the serial interface.
MAX1463 low-power two-channel sensor signal processor 20 ______________________________________________________________________________________ the entire 16-bit content of the dhr register is read out through the do pin by applying 16 successive clock pulses to sclk while cs remains low. dhr is clocked out msb bit first. figure 10 shows the 4-wire mode data read from the dhr register in 4-wire mode, data is transferred into di during the clocking of data out of do. therefore, the last 8 bits clocked into the di pin during this data transfer are latched into the irs register and decoded when cs returns high. when the MAX1463 serial interface is configured in 3- wire mode, the 16-bit dhr data is read out immediately following the command for 3-wire mode enable. figure 11 shows the 3-wire enable command (irs[7:0] = 19h) clocked into di with a subsequent 16-bit read of dhr on do. do remains in high impedance (three-state) until the 3-wire enable command is received. then do goes into low-impedance drive mode during the next low cycle of cs . as sclk is clocked 16 times, the data in dhr is clocked out at do. the 3-wire enable com- mand is the command that sets the MAX1463 ready for output on do on the next low cycle of cs . following the dhr output on the low cycle of cs , the do line returns to high-impedance state until the next 3-wire enable command is received. the MAX1463 can receive an indefinite number of inputs to di without the need for a 3-wire enable command to be received. when the irsd[3:0] nibble is written to the command register (cr), i.e., when irsa[3:0] = 1000, the nibble is decoded and a command operation is initiated. the command register decoding is shown in table 41. when the irsd[3:0] nibble is written to the imr, i.e., when irsa[3:0] = 1001, the nibble is decoded and a command operation is initiated. the imr decoding is shown in table 42. note that after power is applied and the por function completes, the serial interface default is the 3-wire mode for receiving data on di only. the do line is a high- impedance output until the MAX1463 receives either the 4-wire or 3-wire mode command in the imr. in the case of a 3-wire mode command, do switches from a high- impedance state to a driving state only for the next cycle of cs , returning to high-impedance afterwards. all commands, with the exception of programming or erasing the flash memory, are completed within eight internal master clock cycles of cs returning from low to high. this is 4s for a 4mhz oscillator frequency or external clock input (1 internal master clock = 2 exter- nal/internal oscillator periods). flash memory pro- gramming and erasing require additional time of 80s and 4.2ms, respectively. flash memory there are 4096 bytes of programmable/erasable flash memory for cpu program instructions and coefficients storage. in addition, there are 128 bytes of flash mem- ory accessible only by the serial interface for storage of user information data. 20h tmr_control 21h tmr_config prescaler 12-bit counter timeout value mclk figure 6. timer module isrc 33h isrc_control vdd figure 7. current source mode gpion 40h or 41h gpion_control edge or level detect vss 100k ? three-state buffer figure 8. gpio1 and gpio2 modules
MAX1463 low-power two-channel sensor signal processor ______________________________________________________________________________________ 21 these two flash memory locations are separated as partitions. the program/coefficient memory is flash partition 0 and the information memory is flash parti- tion 1. each partition is accessible by the serial inter- face for reading, erasing, and writing data. program/coefficient memory partition 0 is accessible by the cpu as read only, and partition 1 is not accessible by the cpu. the cpu cannot erase or write data to either of the flash memory partitions. flash partition 0 is selected during the por cycle. flash partition 1 is selected by sending the halt cpu command (irs[7:0]=78h) and changing the partition selected by sending the change partition command (irs[7:0]=f8h). a following halt command (irs[7:0]=78h) resets the selected partition to partition 0. modifying the flash contents the MAX1463 flash memory contents must be erased (contents = ffh) before the desired contents can be writ- ten. there is no individual byte-erase command, but either a total-erase command (irs[7:0]=e8h) where all the selected partition is erased (4kb for partition 0 or 128 bytes for partition 1) or a page-erase command (irs[7:0]=d8h), where only 64 bytes are erased, and the page is selected by pfar[11:6]. there are 64 pages in flash partition 0, and only 2 pages in flash partition 1. the programming of the MAX1463 flash memory must follow the procedure below (all the commands are to be sent through the serial interface, and are hexa- decimal values of irs[7:0]): 1) halt the cpu: 78. 2) if partition 1 is to be modified, enter the following command: f8 otherwise, partition 0 is selected. 3) enable the pwrwfl bit on the power-on control register: 1 3 0 2 0 1 0 0 (write 1000 h to dhr[15:0]) d 4 (write d h to pfar[3:0]) 08 (write dhr, 1000h to cpu port pointed by pfar[3:0], port d) 0 3 0 2 3 1 1 0 (write 0031 h to dhr[15:0]) e 4 (write e h to pfar[3:0]) 08 (write dhr, 0031h to cpu port pointed by pfar[3:0], port e) 8 3 0 2 0 1 0 0 (write 8000 h to dhr[15:0]) f 4 (write f h to pfar[3:0]) 08 (write dhr, 8000h to cpu port pointed by pfar[3:0], port f) at this point, all of the MAX1463 analog modules are off. only the bit that enables writing to the flash is enabled. 4) for erasing the whole partition, send the following command: irs0 irsa0 irs1 irsa1 irs2 irsa2 irs3 irsa3 irs4 irsd0 irs5 irsd1 irs6 irsd2 irs7 irsd3 sclk di cs figure 9. serial interface data input irs0 irsa0 irs2 irsa2 irs3 irsa3 irs4 irsd0 irs5 irsd1 irs6 irsd2 irs7 irsd3 irs0 irsa0 irs1 irsa1 irs2 irsa2 irs3 irsa3 irs4 irsd0 irs5 irsd1 irs6 irsd2 irs7 irsd3 dhr15 dhr14 dhr13 dhr12 dhr11 dhr10 dhr9 dhr8 dhr7 dhr6 dhr5 dhr4 dhr3 dhr2 dhr1 dhr0 cs sclk di do irs1 irsa1 figure 10. 4-wire mode data read from dhr register
MAX1463 low-power two-channel sensor signal processor 22 ______________________________________________________________________________________ e8 otherwise, if only a page erase is required, first write pfar[11:6] with the page address, as: 0 7 x 6 x 5 0 4 (write 0xx0 h to pfar[15:0]) note that the 2 lower bits of pfar[7:4] should be zero, and only the upper 2 bits of that nibble should be set to the desired value. then, after writing the page address, send the page-erase command: d8 5) wait at least 4.2ms before sending any other com- mand to allow the necessary time for the erase operation to complete. 6) write the address of the flash byte to be written to pfar[15:0]: 0 7 x 6 x 5 x 4 (write 0xxx h to pfar[15:0]) 7) write the contents of the byte to dhr[7:0]: x 1 x 0 (write xx h to dhr[7:0], high nibble at dhr[7:4]) 8) send the command to execute the flash write: 18 9) repeat steps 6), 7), and 8) for all the bytes to be written. it is not necessary to send the whole address and data for every byte that is written. only the nibbles that are modified in the pfar and in the dhr from previous values must be changed. the time interval between successive write commands (18h) must be at least 80s. 10) if partition 1 was selected in step 2), and the user wants to switch back to partition 0, send the follow ing command: 78 at this point, partition 0 is selected. the user may want to go back to step 4) to program partition 0, or just continue on. 11) disable the pwrwfl bit: 0 3 0 2 0 1 0 0 (write 0000 h to dhr[15:0]) d 4 (write d h to pfar[3:0]) 08 (write dhr, 0000h to cpu port pointed by pfar[3:0], port d) 0 3 0 2 3 1 1 0 (write 0031 h to dhr[15:0]) e 4 (write e h to pfar[3:0]) 08 (write dhr, 0031h to cpu port pointed by pfar[3:0], port e) 8 3 0 2 0 1 0 0 (write 8000 h to dhr[15:0]) f 4 (write f h to pfar[3:0]) 08 (write dhr, 8000h to cpu port pointed by pfar[3:0], port f) alternatively, you can send the reset command, which also clears the pwrwfl bit: b8 reading the flash contents the procedure to read the flash contents is no different from reading any other information from the MAX1463. the flash contents must be copied to the dhr and read through the serial interface (all the commands are hexadecimal values of irs [7:0]): 1) if the cpu is not halted, halt the cpu: 78 2) if partition 1 is to be read, enter the following com- mand: f8 otherwise, partition 0 is selected. 3) write the address of the flash byte to be read to pfar[15:0]: 0 7 x 6 x 5 x 4 (write 0xxx h to pfar[15:0]) 4) copy the contents of flash addressed by pfar to dhr: 38 5) if the interface is configured in 3-wire mode, send 19 to enable do on the next cs cycle. then three- state the di driver, and send 16 sclk pulses on the following cs cycle, and do outputs dhr[15:0]. the flash data is present at dhr[7:0]. see figure 11 for details. if the interface is configured in 4-wire mode, there is no need to enable the do line, as it has already been enabled by a previous irs command 09h. send the 16 sclk pulses and retrieve the data on the do line. 6) repeat steps 3), 4), and 5) for every byte to be read. only the nibbles that are modified in the pfar register are required to be sent. program and coefficient memory the program and coefficient memory, flash partition 0, is addressed by the cpu and by the serial interface sequentially from 0000h (0 dec) to 0fffh (4095 dec). program execution by the cpu always begins at address 0000h and proceeds toward 0fffh in 1-byte increments.
MAX1463 low-power two-channel sensor signal processor ______________________________________________________________________________________ 23 although both the cpu and the serial interface can address a 16-bit field, the flash size only uses 12 bits. therefore, the leading 4 msbs of the address field are ignored. it is advisable to have all leading bits of the 16-bit address in pfar[15:0] set to zero. the flash memory in partition 0 can be erased in indi- vidual 64-byte pages using the page-erase command, or erased in bulk using the all-erase command. the information data memory (partition 1) is unaffected by any operation performed on partition 0. information data memory the information data memory, flash partition 1, is addressed by bytes sequentially from 00h (0) to 7fh (127). the addressed byte should have all leading bits of the 16-bit address in pfar[15:0] set to zero. the flash memory in partition 1 has only two 64-byte pages that can be erased separately using the page- erase command, or erased together using the all-erase command. data in partition 0 is not affected by any operation performed on partition 1. MAX1463 cpu instruction set the MAX1463 cpu has 16 instructions used to perform all calculations for sensor compensation, linearization, and signal output functions. each instruction comprises a 4-bit op code and a 4-bit cpu register address. the op code describes what operation to perform; the reg- ister address describes what register, or registers, to perform the operation on. instruction format all instructions are single-byte instructions with the exception of load data from instruction memory. ldx fetches the 2 following bytes of instruction memory and loads them into a register. this is how calibration and compensation coefficients are stored within the MAX1463. any number of coefficients can be stored in instruction memory. the instruction code format is as follows: instruction set details ldx load register x op-code: 0000 xxxx binary 0xh operation: x-register [pc+1] : [pc+2] pc-register pc + 3 (point to next instruction) cpu cycles required: 3 cycles instruction: loads the next 2 bytes of program memory into cpu register x. register x can be any of the 16 cpu regis- ters. program counter (pc) is incremented twice during the fetches of the next 2 bytes and incremented a third time to point to the next instruction in program memory. two s-complement data format is preserved. no branching occurs. no other registers are affected. clx clear register x op-code: 0001 xxxx binary 1xh operation: x-register 0000h pc-register pc + 1 (point to next instruction) cpu cycles required: 1 cycle description: clear the contents of register x to 0000h. register x can be any of the 16 cpu registers. pc is incremented once to point to the next instruction dhr15 dhr14 dhr13 dhr12 dhr11 dhr10 dhr9 dhr8 dhr7 dhr6 dhr5 dhr4 dhr3 dhr2 dhr1 dhr0 1 irsa0 0 irsa1 0 irsa2 1 irsa3 1 irsd0 0 irsd1 0 irsd2 0 irsd3 cs sclk di do figure 11. 3-wire mode data read from dhr register command op-code (bits 7 4) register op code (bits 3 0) bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 msb lsb
MAX1463 low-power two-channel sensor signal processor 24 ______________________________________________________________________________________ in program memory. two s complement data format is preserved. no branching occurs. no other registers are affected. anx and register x with register a op-code: 0010 xxxx binary 2xh operation: a-register a-register and x-register pc-register pc + 1 (point to next instruction) cpu cycles required: 1 cycle description: perform a 16-bit logical and operation, bit for bit, on the contents of the a-register and the contents of the x- register. store the 16-bit result back into a-register. the previous contents of a-register are overwritten and lost. register x can be any of the 16 cpu registers. pc is incremented once to point to the next instruction in program memory. two s complement data format is not preserved. no branching occurs. no other registers are affected. orx or register x with register a op-code: 0011 xxxx binary 3xh operation: a-register a-register or x-register pc-register pc + 1 (point to next instruction) cpu cycles required: 1 cycle description: perform a 16-bit logical or operation, bit for bit, on the contents of the a-register and the contents of x-regis- ter. store the 16-bit result back into a-register. the pre- vious contents of a-register are overwritten and lost. register x can be any of the 16 cpu registers. pc is incremented once to point to the next instruction in program memory. two s complement data format is not preserved. no branching occurs. no other registers are affected. adx add register x to register a op-code: 0100 xxxx binary 4xh operation: a-register a-register + x-register pc-register pc + 1 (point to next instruction) cpu cycles required: 1 cycle description: perform a 16-bit arithmetic addition of the a-register and the contents of x-register. store the low 16 bits of the result back into a-register. any overflow bit result- ing from the addition operation is lost. the previous contents of a-register are overwritten and lost. register x can be any of the 16 cpu registers. pc is incremented once to point to the next instruction in program memory. two s complement data format is preserved. no branching occurs. no other registers are affected. stx store register x op-code: 0101 xxxx binary 5xh operation: x-register a-register pc-register pc + 1 (point to next instruction) cpu cycles required: 1 cycle description: perform a 16-bit move operation from the a-register into the x-register. the a-register contents are unchanged. the previous contents of x-register are overwritten and lost. register x can be any of the 16 cpu registers. pc is incremented once to point to the next instruction in program memory. two s complement data format is preserved. no branching occurs. no other registers are affected.
MAX1463 low-power two-channel sensor signal processor ______________________________________________________________________________________ 25 slx shift left register x op-code: 0110 xxxx binary 6xh pc-register pc + 1 (point to next instruction) cpu cycles required: 1 cycle description: perform a 16-bit shift-left operation on the contents of x-register. the most significant bit, bit 15, is truncated and lost. if register x is any cpu register other than register r6, then a zero is appended into the lsb, bit 0. if x is cpu register r6, then the data appended into the lsb bit 0 is copied from the msb of register r4. the contents of register r4 are not affected. the operation does not preserve the two s complement sign bit-15. the operation is equivalent to an arithmetic multiplica- tion by 2 on an unsigned integer value stored in regis- ter x. the result is stored back into x-register. the previous contents of x-register are overwritten and lost. register x can be any of the 16 cpu registers. pc is incremented once to point to the next instruction in program memory. two s complement data format is not preserved. no branching occurs. no other registers are affected. srx shift right register x op-code: 0111 xxxx binary 7xh pc-register pc + 1 (point to next instruction) cpu cycles required: 1 cycle description: perform a 15-bit shift-right operation on the contents of x-register, preserving the contents of the two s comple- ment sign bit-15 and propagating the sign bit, bit-15, into bit-14. the least significant bit, bit 0, is truncated and lost. the operation is equivalent to an arithmetic division by 2. the result is stored back into x-register. the previous contents of x-register are overwritten and lost. register x can be any of the 16 cpu registers. pc is incremented once to point to the next instruction in program memory. two s complement data format is preserved. no branching occurs. no other registers are affected. inx increment register x op-code: 1000 xxxx binary 8xh operation: x-register x-register + 1 pc-register pc + 1 (point to next instruction) cpu cycles required: 1 cycle description: perform a 16-bit increment operation on the contents of x-register. should the increment result in an overflow, the overflow bit is truncated and lost. the result is stored back into x-register. the previous contents of x-register are overwritten and lost. 14 15 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 bit : 14 15 13 12 11 10 9 8 7 6 5 4 3 2 1 0 bit : 14 15 13 12 11 10 9 8 7 6 5 4 3 2 1 0 bit : register x operation when x 6h: register r6 register m: r4 operation when x = 6h: 14 15 13 12 11 10 9 8 7 6 5 4 3 2 1 0 bit : register x operation
MAX1463 low-power two-channel sensor signal processor 26 ______________________________________________________________________________________ register x can be any of the 16 cpu registers. pc is incremented once to point to the next instruction in program memory. two s complement data format is preserved. no branching occurs. no other registers are affected. dex decrement register x op-code: 1001 xxxx binary 9xh operation: x-register x-register - 1 pc-register pc + 1 (point to next instruction) cpu cycles required: 1 cycle description: perform a 16-bit decrement operation on the contents of x-register. should the decrement result in an under- flow, the underflow bit is truncated and lost. the result is stored back into x-register. the previous contents of x-register are overwritten and lost. register x can be any of the 16 cpu registers. pc is incremented once to point to the next instruction in program memory. two s complement data format is preserved. no branching occurs. no other registers are affected. ngx negate register x op-code: 1010 xxxx binary axh operation: x-register not x-register pc-register pc-register + 1 (point to next instruction) cpu cycles required: 1 cycle description: perform a 16-bit logical not operation on the contents of x-register. each bit is flipped to its complementary value. the result is stored back into x-register. the previous contents of x-register are overwritten and lost. register x can be any of the 16 cpu registers. pc is incremented once to point to the next instruction in program memory. two s complement data format is not preserved. no branching occurs. no other registers are affected. bpx branch if positive or zero op-code: 1011 xxxx binary bxh operation: if msb(register i) = 0 then: pc-register pc-register + x-register else: pc-register pc + 1 (point to next instruction) cpu cycles required: 1 cycle description: perform a 16-bit check of i-register for a positive (two s complement) or zero value and branch the number of instructions indicated in register-x. the test operation checks the most significant bit, bit-15, for a 0 b and, if true, adds the contents of the x-register to the program counter register. this causes an immediate jump to the new program memory location. the next instruction to execute is fetched from the program memory byte pointed to by the new contents of the pc-register. a 1 b in bit-15 of the i-register is indicative of a negative number (two s complement) to which the test for posi- tive-or-zero value fails. this causes the else operation to be performed and the pc register is incremented by one pointing to the next sequential instruction in pro- gram memory to be executed. the effect bypasses the branch mechanism and normal, sequential, code exe- cution results. the next instruction to execute is fetched from the pro- gram memory byte pointed to by the new contents of the pc-register. the previous contents of pc-register are overwritten and lost. two s complement data format is preserved. branching may occur. no other registers are affected.
bnx branch if not zero op-code: 1100 xxxx binary cxh operation: if i-register 0000h then: pc-register pc-register + x-register else: pc-register pc-register + 1 (point to next instruction) cpu cycles required: 1 cycle description: perform a 16-bit check of the i-register for a nonzero condition and, if true, add the contents of the x-register to the program pointer register. this causes an immedi- ate jump to the new program memory location. the next instruction to execute is fetched from the program memory byte pointed to by the new contents of the pc- register. a 1 b in any bit of the i-register is indicative of a nonzero number to which the test for a zero value fails. this causes the else operation to be performed and the pc-register is incremented by one pointing to the next sequential instruction in program memory to be execut- ed. the effect bypasses the branch mechanism and normal, sequential, code execution results. the next instruction to execute is fetched from the pro- gram memory byte pointed to by the new contents of the pc-register. the previous contents of pc-register are overwritten and lost. two s complement data format is preserved. branching may occur. no other registers are affected. rdx read port x op-code: 1101xxxx binary dxh operation: a-register port-x pc-register pc + 1 (point to next instruction) cpu cycles required: 1 cycle description: perform a 16-bit move operation from port-x to the a- register. the port-x contents are unchanged. the previous contents of a-register are overwritten and lost. the port-x can be any of the cpu ports. pc is incremented once to point to the next instruction in program memory. two s complement data format is preserved. no branching occurs. no other registers are affected. wrx write port x op-code: 1110 xxxx binary exh operation: port-x a-register pc-register pc + 1 (point to next instruction) cpu cycles required: 1 cycle description: perform a 16-bit move operation from the a-register to port-x. the a-register contents are unchanged. the previous contents of port-x are overwritten and lost. the port-x can be any of the cpu ports. pc is incremented once to point to the next instruction in program memory. two s complement data format is preserved. no branching occurs. no other registers are affected. MAX1463 low-power two-channel sensor signal processor ______________________________________________________________________________________ 27
MAX1463 mlt multiply op-code: 1111 0011 binary f3h operation: a-register | m-register n-register x m-register pc-register pc + 1 (point to next instruction) cpu cycles required: 16 cycles description: perform a 16-bit by 16-bit arithmetic multiplication of the m-register and the n-register producing a 32-bit result. the 32-bit result is stored in two 16-bit registers; the a-register receives the most significant word of the result and the m-register receives the least significant word of the result. the a-register must be cleared to zero (clx a) before executing the mlt instruction. the previous contents of a-register are overwritten and lost. the previous contents of m-register are overwritten and lost. the contents of the n-register are not altered. the register op code must be 3h. pc is incremented once to point to the next instruction in program memory. two s complement data format is preserved. no branching occurs. no other registers are affected. low-power two-channel sensor signal processor 28 ______________________________________________________________________________________ address ref alt name function 0h r0 p pointer register. this register contains the address of the instruction or data in flash memory to be fetched. 1h r1 a accumulator register. this register generally contains the result of any operation involving two or more registers. it is the accumulator for the multiregister operation result and can be used effectively to carry data from one computation to the next. the a-register can read and write data to and from any other cpu port or register. 2h r2 general-purpose register. this register is used to hold intermediate calculation results, calculation coefficients, loop counter values, event counter values, comparison limit values, etc. 3h r3 n multiplicand register. this register has a dedicated function when executing a multiply (mlt) instruction, but can be used as a general-purpose register otherwise. the contents of the n-register are not modified by the mlt instruction. 4h r4 m multiplier register. this register has a dedicated function when executing a multiply (mlt) instruction, but can be used as a general-purpose register otherwise. the contents of the m-register are modified by the mlt instruction. the data contents prior to the execution of the mlt instruction are overwritten with the lsbs resulting product, and hence lost. 5h r5 i index register. the branch not zero (bnx) and branch positive (bpx) instructions test the index register, i, for conditions to determine if branching should occur. if the index register tests true for the condition to branch, then the contents of register-x are added to the pointer register, therefore executing a branch in the program. 6h fh r6 rf general-purpose registers. used to hold intermediate calculation results, calculation coefficients, loop counter values, event counter values, comparison limit values, etc. table 1. cpu registers
MAX1463 low-power two-channel sensor signal processor ______________________________________________________________________________________ 29 address ref function 0h ch p0 pc general-purpose ports these ports, p0 pc, can be used to hold intermediate calculation results, often-used calculation coefficients, loop counter values, event counter values, comparison limit values, etc. dh pd module data port. this port is used to transfer data to and from the various functional modules in the MAX1463. data loaded into pd can be transferred to the data, configuration, or control register of any of the functional modules. the data transfer is initiated using the module control port (pf). the contents of pd are not changed during module write operations, but are overwritten by module read operations. eh pe module address port. this port is used to address a module register. a module address is loaded into pe prior to initiating a data-transfer or control function in the module control port. all modules in the MAX1463 are accessed through this indirect addressing method. the contents of pe are not changed by the read or write operations to module registers. only the lower 8 bits are used. the upper 8 bits are not decoded. fh pf module control port. this port initiates an operation on the module addressed by pe. data can be written to, or read from, module registers. specific bits are assigned in the module control port to initiate operations on the MAX1463 modules: bit 15 (ctrl): 1 = initiate action defined in bit 14, 0 = no action initiated. autoreset to zero after operation is completed. bit 14 (rd/ wr ): 1 = read data, 0 = write data. bits 13 0: not decoded. table 2. cpu ports
MAX1463 low-power two-channel sensor signal processor 30 ______________________________________________________________________________________ module name register name address description r/w adc_control 00h initiate conversions and select adc input. r/w adc_data_1 01h result of adc conversion on channel 1 input. r adc_config_1a 02h settings for channel 1 input and conversion. r/w adc_config_1b 03h settings for channel 1 input and conversion. r/w adc_data_2 04h result of adc conversion on channel 2 input. r adc_config_2a 05h settings for channel 2 input and conversion. r/w adc_config_2b 06h settings for channel 2 input and conversion. r/w adc_data_t 07h result of adc conversion on temperature input. r adc_config_ta 08h settings for temperature input and conversion. r/w adc adc_config_tb 09h settings for temperature input and conversion. r/w dop1_data 10h input setting for the analog dac and digital pwm outputs. r/w dop1_control 11h enable and reference selection. r/w dop1 dop1_config 12h select dac or pwm output. r/w dop2_data 13h input setting for the analog dac and digital pwm outputs. r/w dop2_control 14h enable and reference selection. r/w dop2 dop2_config 15h select dac or pwm output. r/w tmr_control 20h initiate timer. r/w timer tmr_config 21h set prescaler value and timeout value. r/w op amp opamp_config 30h set op amps as unity-gain buffers. r/w power po_control 31h turn on power to modules with power-control function. r/w oscillator osc_control 32h trim oscillator frequency, enable clock input/output. r/w isrc cs_control 33h set current source output value. r/w gpio1 gpio1_control 40h enable i/o, set output value, read input value. r/w gpio2 gpio2_control 41h enable i/o, set output value, read input value. r/w table 3. module registers name address description por value adc_control 00h initiate conversions and set signal source. 0000h adc_data_1 01h result of adc conversion on channel 1 input. 0000h adc_config_1a 02h settings for channel 1 input and conversion. 0000h adc_config_1b 03h settings for channel 1 input and conversion. 0070h adc_data_2 04h result of adc conversion on channel 2 input. 0000h adc_config_2a 05h settings for channel 2 input and conversion. 0000h adc_config_2b 06h settings for channel 2 input and conversion. 0070h adc_data_t 07h result of adc conversion on temperature input. 0000h adc_config_ta 08h settings for temperature input and conversion. 0000h adc_config_tb 09h settings for temperature input and conversion. 0070h table 4. adc module registers
MAX1463 low-power two-channel sensor signal processor ______________________________________________________________________________________ 31 bits name description 15 12 unused. 11 8 se[3:0] single-ended signal source multiplexer. se[3] = msb. 7 3 unused. 2 cnvt1 1 = initiate conversion on channel 1 using adc settings specified in registers adc_config_1a and adc_config_1b. the adc result is stored in adc_data_1. cpu is halted during the conversion process. this bit is automatically reset to zero when conversion is completed. 1 cnvt2 1 = initiate conversion on channel 2 using adc settings specified in registers adc_config_2a and adc_config_2b. the adc result is stored in adc_data_2. cpu is halted during the conversion process. this bit is automatically reset to zero when conversion is completed. 0 cnvtt 1 = initiate conversion on temperature sensor using adc settings specified in registers adc_config_ta and adc_config_tb. the adc result is stored in adc_data_t. cpu is halted during the conversion process. the bit is automatically reset to zero when conversion is completed. table 5. adc_control (address = 00h) cnvt1 cnvt2 cnvtt se[3:0] result data_n description 0 0 0 xxxx no measurement. 0 0 1 0000 t convert the temperature sensor signal using the settings in adc_config_ta and adc_config_tb, storing the result in the adc_data_t register. 0 1 x 0000 2 convert the differential signal inp2 inm2 using the settings in adc_config_2a and adc_config_2b, storing the result in the adc_data_2 register. 1 x x 0000 1 convert the differential signal inp1 inm1 using the settings in adc_config_1a and adc_config_1b, storing the result in the adc_data_1 register. 001 bbbb* not used for any setting of se[3:0] 0000. 01x bbbb* 2 convert the single-sided signal indicated by se[3:0] using the settings in adc_config_2a and adc_config_2b, if appropriate, storing the result in the adc_data_2 register. 1xx bbbb* 1 convert the single-sided signal indicated by se[3:0] using the settings in adc_config_1a and adc_config_1b, if appropriate, storing the result in the adc_data_1 register. table 6. initiate conversion (cnvt1, cnvt2, cnvtt) * the value bbbb is any nonzero single-ended setting.
MAX1463 low-power two-channel sensor signal processor 32 ______________________________________________________________________________________ se[3:0] pga range adc +input adc -input description 0001 0.94 vbg v ss bandgap voltage 0010 0.94 240 outnsm v ss output of small op-amp n 0011 0.94 240 outnlg v ss output of large op-amp n 0100 0.7* v dd v ss power-supply voltage 0101 0.7* v ss v ss power-supply ground 0110 0.7* dacn_out using outnsm v ss dacn output through small op-amp n configured as unity-gain buffer 0111 0.7* dacn_out using outnlg v ss dacn output through large op-amp n configured as unity-gain buffer 1000 0.94 240 inpn v ss single-ended input on inpn 1001 0.94 240 inmn v ss single-ended input on inmn table 7. single ended (se[3:0]) * the pga operates at a fixed reduced gain of 0.7v/v to enable conversion of input signals at and near v dd and v ss . this gain set- ting is not selectable. bit name description 15 11 pga1[4:0] programmable gain amplifier setting to use during conversion of channel 1. pga1[4] = msb. 10 8 clk1[2:0] adc clock setting to use during conversion of channel 1. clk1[2] = msb. 7 unused. 6-4 res1[2:0] adc resolution setting to use during conversion of channel 1. res1[2] = msb. 3 co1[3] coarse-offset sign bit. 2-0 co1[2:0] coarse-offset dac setting to use during conversion of channel 1. co1[2] = msb. table 8. adc_config_1a (address = 02h) bit name description 15 7 unused. 6 4 bias1[2:0] adc bias setting to use during conversion of channel 1. bias1[2] = msb. 3 2 unused. 1 0 ref1[1:0] reference select for conversion on channel 1. ref1[1] = msb. table 9. adc_config_1b (address = 03h) bit name description 15 1 pga2[4:0] programmable gain amplifier to use during conversion of channel 2. pga[4] = msb. 10 8 clk2[2:0] adc clock setting to use during conversion of channel 2. clk2[2] = msb. 7 unused. 6 res2[2:0] adc resolution setting to use during conversion of channel 2. res2[2] = msb. 3 co2[3] coarse-offset dac sign bit. 2 0 co2[2:0] coarse-offset dac setting to use during conversion of channel 2. co2[2] = msb. table 10. adc_config_2a (address = 05h)
MAX1463 low-power two-channel sensor signal processor ______________________________________________________________________________________ 33 bit name description 15 7 unused. 6 4 bias2[2:0] adc bias setting to use during conversion of channel 2. bias2[2] = msb. 3 2 unused. 1 0 ref2[1:0] reference select for conversion on channel 2. ref2[2] = msb. table 11. adc_config_2b (address = 06h) bits name description 15 1 unused. 10 8 clkt[2:0] adc clock setting to use during conversion of the temperature sensor. clkt[2] = msb. 7 unused. 6 4 rest[2:0] adc resolution setting to use during conversion of the temperature sensor. rest[2] = msb. 3 cot[3] coarse offset dac sign bit. 2 0 cot[2:0] coarse offset dac setting to use during conversion of the temperature sensor. cot[2] = msb. table 12. adc_config_ta (address = 08h) bits name description 15 7 unused. 6 4 biast[2:0] adc bias setting to use during conversion of the temperature sensor. biast[2] = msb. 3 0 unused. table 13. adc_config_tb (address = 09h) pgan[4:0] gain (v/v) 00000 0.94 00001 7.4 00010 15 00011 22 00100 30 00101 37 00110 44 00111 52 01000 60 01010 73 01100 85 01110 95 10000 105 10100 133 11000 174 11100 182 11110 240 table 14. programmable gain amplifier (pgan[4:0], where n = 1 or 2) clkn[2:0] divisor n f adc (hz) 000 4 1m 001 8 500k 010 16 250k 011 32 125k 100 64 62.5 k 101 128 31.25k 110 256 15.625k 111 512 7.8125k table 15. adc clock (clkn[2:0], where n = 1, 2, or t; f clk = 4mhz)
MAX1463 low-power two-channel sensor signal processor 34 ______________________________________________________________________________________ resn[2:0] resolution (bits) no. of f adc clocks per conversion 000 9 256 001 10 320 010 12 512 011 13 640 100 14 800 101 15 1280 110 16 2048 table 16. adc resolution (resn[2:0], where n = 1, 2, or t) coarse offset added as % of adc reference input * pgan = 0.94 60 pgan = 73 105 pgan = 133 240 con[3:0] 00000 to 01000 01010 to 10000 10100 to 11110 0111 +135 +266 +481 0110 +116 +229 +410 0101 +98 +193 +341 0100 +79 +158 +277 0011 +60 +117 +210 0010 +42 +79 +140 0001 +23 +44 +76 0000 +5 +9 +8 1000 +12 +23 +33 1001 -7 -15 -36 1010 -26 -50 -100 1011 -44 -87 -169 1100 -64 -130 -239 1101 -81 -166 -305 1110 -100 -202 -374 1111 -117 -238 -495 table 18. coarse-offset dac (3 bits plus sign, n = 1, 2, or t) conversion time (ms) resolution (bits) clkn[2:0] = 000 clkn[2:0] = 100 clkn[2:0] = 111 9 0.256 4.096 32.768 10 0.320 5.120 40.960 12 0.512 8.192 65.536 13 0.640 10.240 81.920 14 0.800 12.800 102.400 15 1.280 20.480 163.840 16 2.048 32.768 262.140 table 17. adc conversion time (resn[2:0] and clkn[2:0], where n = 1, 2, or t) biasn[2:0] fraction of full bias current maximum adc clock frequency (khz) clkn[2:0] 000 1/8 125 011 001 2/8 250 011 010 3/8 250 010 011 4/8 500 010 100 5/8 500 001 101 6/8 500 001 110 7/8 1 mhz 000 111 8/8 1 mhz 000 table 19. adc bias current (biasn[2:0], where n = 1, 2, or t) refn[1:0] adc reference 00 v dd 01 v ref (external) 10 vbg x 4 (pseudo 5v) table 20. adc reference voltage source (refn[1:0], where n = 1 or 2) * measured at the adc input.
MAX1463 low-power two-channel sensor signal processor ______________________________________________________________________________________ 35 dop configuration pwrdac pwrop seldac selpwm endac enpwm buf dac off, pwm off, op amp off. 0 0 x x 0 0 x dac off, pwm off, op amp on . ampnp and ampnm routed to lg op amp. 010x000 dac off, pwm off, op amp on . lg op amp configured as unity-gain buffer. 010x001 dac off, pwm off, op amp on . ampnp and ampnm routed to sm op amp. 011x000 dac off, pwm off, op amp on . sm op amp configured as unity-gain buffer. 011x001 dac off, pwm on , op amp off. pwm output on outnsm. 000 001x dac off, pwm on , op amp off. pwm output on outnlg. 000 101x dac off, pwm on , op amp on . ampnp and ampnm routed to lg op amp. pwm output on outnsm. 010 0010 dac off, pwm on , op amp on . lg op amp configured as unity-gain buffer. pwm output on outnsm. 010 0011 dac off, pwm on , op amp on . ampnp and ampnm routed to sm op amp. pwm output on outnlg. 011 1010 dac off, pwm on , op amp on . sm op amp configured as unity-gain buffer. pwm output on outnlg. 011 1011 dac on , pwm off, op amp off. dac output on outnsm. 100x10x dac on , pwm off, op amp off. dac output on outnlg. 101x10x dac on , pwm off, op amp on . dac output on outnsm. ampnp and ampnm routed to lg op amp. 110x100 table 21. dopn configuration options
MAX1463 low-power two-channel sensor signal processor 36 ______________________________________________________________________________________ dop configuration pwrdac pwrop seldac selpwm endac enpwm buf dac on , pwm off, op amp on . dac output on outnsm. lg op amp configured as unity-gain buffer. 110x101 dac on , pwm off, op amp on . dac output on outnlg. ampnp and ampnm routed to sm op amp. 111x100 dac on , pwm off, op amp on . dac output on outnlg. sm op amp configured as unity-gain buffer. 111x101 dac on , pwm on , op amp off. dac output on outnsm. pwm output on outnlg. 1x0 111x dac on , pwm on , op amp off. dac output on outnlg. pwm output on outnsm. 1x1 011x table 21. dopn configuration options (continued) name address description por value dop1_data 10h dac1/pwm1 input data. 0000 dop1_control 11h initiate dac1 and/or pwm1 conversions. 0000 dop1_config 12h dac1/pwm1 output and dac 1 reference selection. 0000 dop2_data 13h dac2/pwm2 input data. 0000 dop2_control 14h initiate dac2 and/or pwm2 conversions. 0000 dop2_config 15h dac2/pwm2 output and dac 2 reference selection. 0000 opamp_config 30h settings for op amps in dopn modules. 0000 table 22. dop module registers bit name description 15 5 unused. 4 enpwm1 enable pulse-width modulator 1: 1 = pwm1 active, 0 = pwm1 inactive. 3 1 unused. 0 endac1 enable digital-to-analog converter 1: 1 = dac1 active, 0 = dac1 inactive. table 23. dop1_control (address = 11h)
MAX1463 low-power two-channel sensor signal processor ______________________________________________________________________________________ 37 bit name description 15 9 unused. 8 selpwm1 select pwm1 output: 1 = out1lg, 0 = out1sm. 7 5 unused. 4 seldac1 select dac1 output: 1 = out1lg (large op-amp buffer), 0 = out1sm (small op-amp buffer). 3 1 unused. 0 selref1 select voltage reference for dac1: 0 = v dd , 1 = 2 x v ref . table 24. dop1_config (address = 12h) bit name description 15 5 unused. 4 enpwm2 enable pulse width modulator 2: 1 = pwm2 active, 0 = pwm2 inactive. 3 1 unused. 0 endac2 enable digital-to-analog converter 2: 1 = dac2 active, 0 = dac2 inactive. table 25. dop2_control (address = 14h) bit name description 15 9 unused. 8 selpwm2 select pwm2 output: 1 = out2lg, 0 = out2sm. 7 5 unused. 4 seldac2 select dac2 output: 1 = out2lg (large op-amp buffer), 0 = out2sm (small op-amp buffer). 3 1 unused. 0 selref2 select voltage reference for dac2: 0 = v dd , 1 = 2 x v ref . table 26. dop2_config (address = 15h) bit name description 15 2 unused. 1 buf2 1 = buffer mode of both large and small op amps of dop2, 0 = normal. 0 buf1 1 = buffer mode of both large and small op amps of dop1, 0 = normal. table 27. opamp_config (address = 30h)
MAX1463 low-power two-channel sensor signal processor 38 ______________________________________________________________________________________ bits name description 15 6 unused. 5 out1 out1 value is driven onto the gpio1 pin when the output driver is enabled. 4 en1 enable the output driver; 1 = enabled, 0 = disabled, and out three-stated. 3 in1 when edge1 = 0: the value input on gpio1 is clocked into this bit (notes 1, 2). when edge1 = 1: an edge detection on gpio1 causes a 1 to be clocked into this bit. 2 clr1 clear in1 bit; 1 = clear in1 to 0, 0 = in1 retains its status (note 3). 1 inv1 when edge1 = 0: invert the logic value in1; 1 = invert input, 0 = do not invert. when edge1 = 1: select edge capture type; 1 = falling edge detect; 0 = rising edge detect. 0 edge1 select level or edge detection at in1; 1 = detect edges, 0 = detect and track logic levels. table 28. gpio1_control (address = 40h) note 1: a pulse or level must remain on gpion for four periods of f osc to be latched into in. note 2: the clrn bit must be cleared to zero to reenable gpio to value tracking. note 3: the clrn bit must be cleared to zero to reenable gpio edge detection. bits name description 15 6 unused. 5 out2 out2 value is driven onto the gpio2 pin when the output driver is enabled. 4 en2 enable the output driver; 1 = enabled, 0 = disabled and out three-stated. 3 in2 when edge2 = 0: the value input on gpio2 is clocked into this bit. (notes 1, 2) when edge2 = 1: an edge detection on gpio2 causes a 1 to be clocked into this bit. 2 clr2 clear in2 bit; 1 = clear in2 to 0, 0 = in2 retains its status. [3] 1 inv2 when edge2 = 0: invert the logic value in2; 1 = invert input, 0 = do not invert. when edge2 = 1: select edge capture type; 1 = falling edge detect; 0 = rising edge detect. 0 edge2 select level or edge detection at in2; 1 = detect edges, 0 = detect and track logic levels. table 29. gpio2_control (address = 41h) note 1: a pulse or level must remain on gpion for four periods of f osc to be latched into in. note 2: the clrn bit must be cleared to zero to reenable gpio to value tracking. note 3: the clrn bit must be cleared to zero to reenable gpio edge detection. bit name description 15 tmdn timer done bit set by the counter; 1 = timeout value reached, 0 = timeout not reached. read-only bit. 14 tmen timer enable bit; a 1 written to tmen resets tmdn to zero and starts counter. tmen is reset to zero by the counter when timeout value is reached. 13 1 unused. 0 enahalt enable cpu halt; 1 = cpu halted for duration of timer interval, 0 = cpu not halted. table 30. tmr_control (address = 20h)
MAX1463 low-power two-channel sensor signal processor ______________________________________________________________________________________ 39 bit name description 15 12 ps[3:0] prescaler setting to use during the timing interval. ps[3 ] = msb. 11 0 to[11:0] timeout value to use during the timing interval. to[11] = msb. table 31. tmr_config (address = 21h) ps[3:1] ps[0] prescaler n 000 0 1 001 0 2 010 0 4 011 0 8 100 0 16 101 0 32 110 0 64 111 0 128 000 1 3 001 1 6 010 1 12 011 1 24 100 1 48 101 1 96 110 1 192 111 1 384 table 32. timer prescaler settings (ps[3:0]) bits name description 15 3 unused. 2 0 isrc[2:0] current source setting. isrc[2] = msb. table 33. current source_control (address = 33h) isrc[2:0] isrc (a) 000 0 001 -167 010 -334 011 -501 100 -668 101 -835 110 -1002 111 -1169 table 34. current-source settings (isrc[2:0])
MAX1463 low-power two-channel sensor signal processor 40 ______________________________________________________________________________________ bits name description 15 13 unused. 12 pwrwfl power for writing and erasing flash memory: 1 = power enabled, 0 = disabled. 11 9 unused. 8 pwra2d power for adc: 1 = power enabled, 0 = disabled. 7 6 unused. 5 pwrdac2 power for dac2 in dop2: 1 = power enabled, 0 = disabled. 4 pwrdac1 power for dac1 in dop1: 1 = power enabled, 0 = disabled. 3 2 unused. 1 pwrop2 power for both large and small op amps in dop2: 1 = power enabled, 0 = disabled, op-amp outputs are high impedance.* 0 pwrop1 power for both lg and sm op amps in dop1: 1 = power enabled, 0 = disabled, op-amp outputs are high impedance.* table 35. power-on control (address = 31h) * whenever the dacs are enabled, the large and/or small op amps are automatically powered-up and configured as buffers, regard- less of the state of the pwropn and bufn bits. bits name description 15 13 unused. 12 8 osc[4:0] oscillator trim setting. osc[4] = msb. 7 6 unused. 5 4 reserved 0. 3 1 unused. 0 enckout enable clock output: 1 = enable internal clock output on ckio based on cksel pin, 0 = disable. table 36. oscillator control (address = 32h)
MAX1463 low-power two-channel sensor signal processor ______________________________________________________________________________________ 41 osc[4:0] binary decimal % change from nominal clock frequency (%) 01111 15 +43.7 01110 14 +42.2 01101 13 +40.1 01100 12 +38.4 01011 11 +35.2 01010 10 +32.8 01001 9 +28.8 01000 8 +25.5 00111 7 +17.7 00110 6 +14.1 00101 5 +10.0 00100 4 +8.4 00011 3 +5.4 00010 2 +3.6 00001 1 +1.4 00000 0 0 11111 -1 -3.4 11110 -2 -4.9 11101 -3 -7.2 11100 -4 -9.1 11011 -5 -12.6 11010 -6 -15.1 11001 -7 -18.5 11000 -8 -21.0 10111 -9 -25.3 10110 -10 -27.2 10101 -11 -29.9 10100 -12 -32.1 10011 -13 -35.8 10010 -14 -38.1 10001 -15 -40.9 10000 -16 -43.0 table 37. oscillator trim settings (two s complement) enckout cksel (pin) ckio description x 0 input internal oscillator is halted. an external clock must be supplied to ckio pin. 01 high impedance internal oscillator is running. ckio output driver is disabled. 1 1 output internal oscillator is running. ckio output driver is enabled driving clock output. table 38. internal oscillator and ckio control
MAX1463 low-power two-channel sensor signal processor 42 ______________________________________________________________________________________ bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 register 00h adc_control x x x x se[3] se[2] se[1] se[0] x x x x x cnvt1 cnvt2 cnvtt register 01h adc_data_1 (for channel input 1, uncompensated, and read only register) msb lsb register 02h adc_config_1a (for channel 1) pga1[4] pga1[3] pga1[2] pga1[1] pga1[0] clk1[2] clk1[1] clk1[0] x res1[2] res1[1] res1[0] co1[3] co1[2] co1[1] co1[0] register 03h adc_config_1b (for channel 1) x x x x x x x x x bias1[2] bias1[1] bias1[0] x x ref1[1] ref1[0] register 04h adc_data_2 (for channel input 1, uncompensated, and read only register) msb lsb register 05h adc_config_2a (for channel 2a) pga2[4] pga2[3] pga2[2] pga2[1] pga2[0] clk2[2] clk2[1] clk2[0] x res2[2] res2[1] res2[0] co2[3] co2[2] co2[1] co2[0] register 06h adc_config_2b (for channel 2b) x x x x x x x x x bias2[2] bias2[1] bias2[0] x x ref2[1] ref2[0] register 07h adc data_t (for internal temperature input, uncompensated, and read only register) msb lsb register 08h adc_config_ta (for internal temperature input ta) x x x x x clkt[2] clkt[1] clkt[0] x rest[2] rest[1] rest[0] cot[3] cot[2] cot[1] cot[0] register 09h adc_config_tb (for internal temperature input tb) x x x x x x x x x biast[2] biast[1] biast[0] x x x x register 10h dop1 data (for dac/pwm 1) msb lsb register 11h dop1 control (for dac/pwm 1) x x x x x x x x x x x enpwm1 x x x enda c1 register 12h dop1 configuration (for dac/pwm 1) x x x x x x x selpw m1 x x x selda c1 x x x selre f1 register 13h dop2 data (for dac/pwm 2) msb lsb register 14h dop2 control (for dac/pwm 2) x x x x x x x x x x x enpwm 2 x x x enda c2 register 15h dop2 configuration (for dac/pwm 2) x x x x x x x selpw m2 x x x selda c2 x x x selre f2 register 20h timer control tmdn tmen x x x x x x x x x x x x x enaha lt table 39. module registers summary
MAX1463 low-power two-channel sensor signal processor ______________________________________________________________________________________ 43 register 21h timer configuration ps[3] ps[2] ps[1] ps[0] to[11] to[10] to[9] to[8] to[7] to[6] to[5] to[4] to[3] to[2] to[1] to[1] register 30h op amp configuration x x x x x x x x x x x x x x buf2 buf1 register 31h power on control x x x pwrw fl x x x pwra2 d x x pwrd ac2 pwrd ac1 x x pwro p2 pwro p1 register 32h oscillator control x x x osc[4] osc[3] osc[2] osc[1] osc[0] x x x x x x x enck out register 33h current source control x x x x x x x x x x x x x isrc[2] isrc[1] isrc[0] register 40h gpio1 control x x x x x x x x x x out1 en1 in1 clr1 inv1 edge1 register 41h gpio2 control x x x x x x x x x x out2 en2 in2 clr2 inv2 edge2 table 39. module registers summary (continued) irsa[3:0] register nibble addressed description 0000 dhr[3:0] write irsd[3:0] to dhr[3:0] 0001 dhr[7:4] write irsd[3:0] to dhr[7:4] 0010 dhr[11:8] write irsd[3:0] to dhr[11:8] 0011 dhr[15:12] write irsd[3:0] to dhr[15:12] 0100 pfar[3:0] write irsd[3:0] to pfar[3:0] 0101 pfar[7:4] write irsd[3:0] to pfar[7:4] 0110 pfar[11:8] write irsd[3:0] to pfar[11:8] 0111 pfar[15:12] write irsd[3:0] to pfar[15:12] 1000 cr[3:0] write irsd[3:0] to cr[3:0] 1001 imr[3:0] write irsd[3:0] to ir[3:0] 1010 1111 unused table 40. internal register set address (irsa) decoding
MAX1463 low-power two-channel sensor signal processor 44 ______________________________________________________________________________________ cr description cpu halted 0000 write 16-bit dhr contents into the cpu port specified by pfar[3:0]. no [1] 0001 write 8-bit dhr[7:0] contents into flash memory location specified by pfar[11:0]. note 2. yes 0010 read 16-bit cpu port specified by pfar[3:0] into dhr. no [1] 0011 read 8-bit flash location specified by pfar[11:0] into dhr[7:0]. yes 0100 read 16-bit cpu accumulator register (a) into dhr. yes 0101 read 8-bit flash location specified by the cpu program counter (pc) (cpu instruction or data) to dhr[7:0]. yes 0110 read 16-bit cpu pc to dhr. yes 0111 halt the cpu. no 1000 start the cpu, i.e., clear the halt cpu bit from the current pc location. yes 1001 single step the cpu. only one cpu clock cycle is executed. yes 1010 reset the pc to zero. yes 1011 reset the modules, flash controller, and cpu registers d, e, f. yes 1100 no operation. 1101 erase a 64-byte page of flash as specified by pfar[11:6]. yes 1110 erase the entire flash partition (4kb, ps0, or 128 bytes, ps1). yes 1111 change from flash partition ps0 to flash partition ps1 (128 byte auxiliary). a subsequent halt cpu command resets the partition selection back to ps0. yes table 41. command register (cr) decoding irsd description 0000 place the MAX1463 into a 4-wire serial interface (di cannot be tied to do). 0001 place the MAX1463 into a 3-wire serial interface (di can be externally tied to do). 0010 1111 unused. table 42. interface mode register (imr) decoding note 1: reading and writing the cpu ports by the serial interface is allowed while the cpu is executing its program. in the case of simultaneous access of the ports by both the cpu and the serial interface, the cpu has priority. although this procedure is allowed, it is not recommended, as the serial interface may change values previously written by the cpu. if a snapshot of the ports and module register contents is required while the cpu is running, halt the cpu, read the contents of the ports and/or module registers, and restore the original port/module register values prior to starting the cpu again. note 2: the pwrwfl bit in the power-on control register (31h) must be enabled for a write operation to occur. see the flash memory section for further details on writing the flash memory.
MAX1463 low-power two-channel sensor signal processor ______________________________________________________________________________________ 45 op code (hex) mnemonic operation two s comp no. of registers involved no. of cycles no. of bytes 0x ldx load register x from program memory y 1 3 3 1x clx clear x-reg y 1 1 1 2x anx a-reg = a-reg and x-reg n 2 1 1 3x orx a-reg = a-reg or x-reg n 2 1 1 4x adx a-reg = a-reg add x-reg y 2 1 1 5x stx x-reg = a-reg y 2 1 1 6x slx shift left x-reg n 1 or 2 1 1 7x srx shift right x-reg propagating sign bit y 1 1 1 8x inx x-reg = x-reg + 1 y 1 1 1 9x dex x-reg = x-reg - 1 y 1 1 1 ax ngx x-reg = not x-reg n 1 1 1 bx bpx branch positive i-reg by amount in x-reg y211 cx bnx branch not zero i-reg by amount in x-reg y211 dx rdx a-reg = cpu port-x y 1 1 1 ex wrx cpu port-x = a-reg y 1 1 1 f3 mlt a-reg | m-reg = m-reg multiplied by n- reg; register op code must be 3h. y 3 16 1 table 43. instruction set
MAX1463 low-power two-channel sensor signal processor 46 ______________________________________________________________________________________ power- on reset 4kb flash memory 16-bit cpu serial interface v dd v ddf v ss sclk di do cs external reference input vref vbg bandgap reference output digital i/o ckio cksel gpio2 gpio1 isrc adc co dac temp sensor inp1 inm1 inp2 inm2 pga mux out2sm amp2m out2lg amp2p dac 2 pwm 2 lg sm out1sm amp1m out1lg amp1p dac 1 pwm 1 lg sm vdd isrc functional diagram chip information transistor count: 70,921 (not including flash) process: cmos substrate connected to: v ss
MAX1463 low-power two-channel sensor signal processor ______________________________________________________________________________________ 47 inp1 inm1 inp2 inm2 co dac ref temperature sensor vss vbg vdd vbg x 4 vref adc inmn vbg outnsm outnlg v dd v ss dacnout via outnsm inpn 1 2 3 4 5 6 7 8 9 no. single ended dacnout via outnlg 00h adc_control 08h adc_config_ta 07h adc_data_t 06h adc_config_2b 09h adc_config_tb 02h adc_config_1a 05h adc_config_2a 04h adc_data_2 03h 01h adc_data_1 adc_config_1b pga m u x vss m u x isrc isrc isrc module adc module 33h isrc_control vdd flash memory (4kb) serial interface sclk di do cs r0 pointer (p) r1 accumulator (a) r2 r3 multiplicand (n) r4 multiplier (m) r5 index (i) r6 r7 r8 r9 ra rb rc rd re rf p0 p1 p2 p1 p3 p4 p5 p6 p7 p8 pa pb pc pd pe pf cpu registers instruction cpu flash data address cpu ports power-on reset v dd v ddf v ss bandgap reference vbg external reference input vref cksel ckio 32h osc_control vdd 4mhz oscillator 2 mclk en enckout out detailed block diagram
MAX1463 low-power two-channel sensor signal processor 48 ______________________________________________________________________________________ dop1 module gpio1 gpio2 dac1 10h dop1_data 12h dop1_config 30h opamp_config 11h dop1_control ref pwm1 sw0 sw1 sw2 sw3 sw4 sw5 sw6 sw7 sw8 sw9 vref x 2 vdd out1sm amp1m amp1p out1lg sw10 sw11 sm1 lg1 dop2 module dac2 13h dop2_data 15h dop2_config 30h opamp_config 14h dop2_control ref pwm2 sw0 sw1 sw2 sw3 sw4 sw5 sw6 sw7 sw8 sw9 vref x 2 vdd out2sm amp2m amp2p out2lg sw10 sw11 sm2 lg2 20h tmr_control 21h tmr_config prescaler 12-bit counter time out value mclk 40h gpion_control edge or level detect vss 100k ? three-state buffer 41h gpion_control edge or level detect vss 100k ? three-state buffer detailed block diagram (continued)
MAX1463 low-power two-channel sensor signal processor maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a maxim product. no circu it patent licenses are implied. maxim reserves the right to change the circuitry and specifications without notice at any time. maxim integrated products, 120 san gabriel drive, sunnyvale, ca 94086 408-737-7600 ____________________ 49 ? 2002 maxim integrated products printed usa is a registered trademark of maxim integrated products. package information (the package drawing(s) in this data sheet may not reflect the most current specifications. for the latest package outline info rmation, go to www.maxim-ic.com/packages .) ssop.eps package outline, ssop, 5.3 mm 1 1 21-0056 c rev. document control no. approval proprietary information title: notes: 1. d&e do not include mold flash. 2. mold flash or protrusions not to exceed .15 mm (.006"). 3. controlling dimension: millimeters. 4. meets jedec mo150. 5. leads to be coplanar within 0.10 mm. 7.90 h l 0 0.301 0.025 8 0.311 0.037 0 7.65 0.63 8 0.95 max 5.38 millimeters b c d e e a1 dim a see variations 0.0256 bsc 0.010 0.004 0.205 0.002 0.015 0.008 0.212 0.008 inches min max 0.078 0.65 bsc 0.25 0.09 5.20 0.05 0.38 0.20 0.21 min 1.73 1.99 millimeters 6.07 6.07 10.07 8.07 7.07 inches d d d d d 0.239 0.239 0.397 0.317 0.278 min 0.249 0.249 0.407 0.328 0.289 max min 6.33 6.33 10.33 8.33 7.33 14l 16l 28l 24l 20l max n a d e a1 l c h e n 1 2 b 0.068

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